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yaml
---
r: 296815
b: refs/heads/master
c: b4a6dbd
h: refs/heads/master
i:
  296813: ba3a996
  296811: 8465dd1
  296807: 1db17b7
  296799: 29ada73
v: v3
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Mattias Nilsson authored and Samuel Ortiz committed Mar 6, 2012
1 parent a690733 commit 36dcffd
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Showing 4 changed files with 172 additions and 32 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 6f53d10dda1323c17fb09063c4df2c22754bf8aa
refs/heads/master: b4a6dbd5b7bad00ee4004443287468abddb96538
36 changes: 17 additions & 19 deletions trunk/drivers/mfd/db8500-prcmu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -417,8 +417,8 @@ static struct {
static atomic_t ac_wake_req_state = ATOMIC_INIT(0);

/* Spinlocks */
static DEFINE_SPINLOCK(prcmu_lock);
static DEFINE_SPINLOCK(clkout_lock);
static DEFINE_SPINLOCK(gpiocr_lock);

/* Global var to runtime determine TCDM base for v2 or v1 */
static __iomem void *tcdm_base;
Expand Down Expand Up @@ -639,32 +639,30 @@ int db8500_prcmu_set_display_clocks(void)
return 0;
}

/**
* prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
*/
void prcmu_enable_spi2(void)
u32 db8500_prcmu_read(unsigned int reg)
{
return readl(_PRCMU_BASE + reg);
}

void db8500_prcmu_write(unsigned int reg, u32 value)
{
u32 reg;
unsigned long flags;

spin_lock_irqsave(&gpiocr_lock, flags);
reg = readl(PRCM_GPIOCR);
writel(reg | PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR);
spin_unlock_irqrestore(&gpiocr_lock, flags);
spin_lock_irqsave(&prcmu_lock, flags);
writel(value, (_PRCMU_BASE + reg));
spin_unlock_irqrestore(&prcmu_lock, flags);
}

/**
* prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
*/
void prcmu_disable_spi2(void)
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
u32 reg;
u32 val;
unsigned long flags;

spin_lock_irqsave(&gpiocr_lock, flags);
reg = readl(PRCM_GPIOCR);
writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR);
spin_unlock_irqrestore(&gpiocr_lock, flags);
spin_lock_irqsave(&prcmu_lock, flags);
val = readl(_PRCMU_BASE + reg);
val = ((val & ~mask) | (value & mask));
writel(val, (_PRCMU_BASE + reg));
spin_unlock_irqrestore(&prcmu_lock, flags);
}

struct prcmu_fw_version *prcmu_get_fw_version(void)
Expand Down
44 changes: 32 additions & 12 deletions trunk/include/linux/mfd/db8500-prcmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,24 @@
#define __MFD_DB8500_PRCMU_H

#include <linux/interrupt.h>
#include <linux/bitops.h>

/*
* Registers
*/
#define DB8500_PRCM_GPIOCR 0x138
#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)
#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)
#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)
#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)

#define DB8500_PRCM_LINE_VALUE 0x170
#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)

#define DB8500_PRCM_DSI_SW_RESET 0x324
#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)

/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */

Expand Down Expand Up @@ -552,8 +570,6 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
void prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
void db8500_prcmu_modem_reset(void);
void prcmu_enable_spi2(void);
void prcmu_disable_spi2(void);

int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
int db8500_prcmu_enable_a9wdog(u8 id);
Expand Down Expand Up @@ -582,6 +598,10 @@ int db8500_prcmu_get_ape_opp(void);
int db8500_prcmu_set_ddr_opp(u8 opp);
int db8500_prcmu_get_ddr_opp(void);

u32 db8500_prcmu_read(unsigned int reg);
void db8500_prcmu_write(unsigned int reg, u32 value);
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);

#else /* !CONFIG_MFD_DB8500_PRCMU */

static inline void db8500_prcmu_early_init(void) {}
Expand Down Expand Up @@ -703,16 +723,6 @@ static inline void db8500_prcmu_modem_reset(void) {}

static inline void db8500_prcmu_system_reset(u16 reset_code) {}

static inline int prcmu_enable_spi2(void)
{
return 0;
}

static inline int prcmu_disable_spi2(void)
{
return 0;
}

static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
Expand Down Expand Up @@ -805,6 +815,16 @@ static inline int db8500_prcmu_get_arm_opp(void)
return 0;
}

static inline u32 db8500_prcmu_read(unsigned int reg)
{
return 0;
}

static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}

static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
u32 value) {}

#endif /* !CONFIG_MFD_DB8500_PRCMU */

#endif /* __MFD_DB8500_PRCMU_H */
122 changes: 122 additions & 0 deletions trunk/include/linux/mfd/dbx500-prcmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -480,6 +480,30 @@ static inline int prcmu_stop_temp_sense(void)
return db8500_prcmu_stop_temp_sense();
}

static inline u32 prcmu_read(unsigned int reg)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_read(reg);
}

static inline void prcmu_write(unsigned int reg, u32 value)
{
if (cpu_is_u5500())
return;
else
db8500_prcmu_write(reg, value);
}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
if (cpu_is_u5500())
return;
else
db8500_prcmu_write_masked(reg, mask, value);
}

static inline int prcmu_enable_a9wdog(u8 id)
{
if (cpu_is_u5500())
Expand Down Expand Up @@ -668,6 +692,104 @@ static inline int prcmu_stop_temp_sense(void)
return 0;
}

static inline u32 prcmu_read(unsigned int reg)
{
return 0;
}

static inline void prcmu_write(unsigned int reg, u32 value) {}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}

#endif

static inline void prcmu_set(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, bits);
}

static inline void prcmu_clear(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, 0);
}

#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)

/**
* prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
*/
static inline void prcmu_enable_spi2(void)
{
if (cpu_is_u8500())
prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
}

/**
* prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
*/
static inline void prcmu_disable_spi2(void)
{
if (cpu_is_u8500())
prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
}

/**
* prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
* and UARTMOD on OtherAlternateC3.
*/
static inline void prcmu_enable_stm_mod_uart(void)
{
if (cpu_is_u8500()) {
prcmu_set(DB8500_PRCM_GPIOCR,
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
}
}

/**
* prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
* and UARTMOD on OtherAlternateC3.
*/
static inline void prcmu_disable_stm_mod_uart(void)
{
if (cpu_is_u8500()) {
prcmu_clear(DB8500_PRCM_GPIOCR,
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
}
}

/**
* prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
*/
static inline void prcmu_enable_stm_ape(void)
{
if (cpu_is_u8500()) {
prcmu_set(DB8500_PRCM_GPIOCR,
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
}
}

/**
* prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
*/
static inline void prcmu_disable_stm_ape(void)
{
if (cpu_is_u8500()) {
prcmu_clear(DB8500_PRCM_GPIOCR,
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
}
}

#else

static inline void prcmu_enable_spi2(void) {}
static inline void prcmu_disable_spi2(void) {}
static inline void prcmu_enable_stm_mod_uart(void) {}
static inline void prcmu_disable_stm_mod_uart(void) {}
static inline void prcmu_enable_stm_ape(void) {}
static inline void prcmu_disable_stm_ape(void) {}

#endif

/* PRCMU QoS APE OPP class */
Expand Down

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