Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 149851
b: refs/heads/master
c: d8baa93
h: refs/heads/master
i:
  149849: 156a733
  149847: 30c3be1
v: v3
  • Loading branch information
Sujith authored and John W. Linville committed Apr 22, 2009
1 parent 66bc6d2 commit 380c69f
Show file tree
Hide file tree
Showing 11 changed files with 116 additions and 130 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 6ed6a05e5c8061cdcd69a418c90c5f11979ce650
refs/heads/master: d8baa9392666d1c50ef42e9f6fbbb0cf536327b9
8 changes: 3 additions & 5 deletions trunk/drivers/net/wireless/ath9k/ani.c
Original file line number Diff line number Diff line change
Expand Up @@ -569,8 +569,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"phyCnt1 0x%x, resetting "
"counter value to 0x%x\n",
phyCnt1,
aniState->ofdmPhyErrBase);
phyCnt1, aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1,
aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_MASK_1,
Expand All @@ -580,8 +579,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"phyCnt2 0x%x, resetting "
"counter value to 0x%x\n",
phyCnt2,
aniState->cckPhyErrBase);
phyCnt2, aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2,
aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_MASK_2,
Expand Down Expand Up @@ -667,7 +665,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
u32 cc = REG_READ(ah, AR_CCCNT);

if (cycles == 0 || cycles > cc) {
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
"cycle counter wrap. ExtBusy = 0\n");
good = 0;
} else {
Expand Down
7 changes: 2 additions & 5 deletions trunk/drivers/net/wireless/ath9k/beacon.c
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ static int ath_beaconq_config(struct ath_softc *sc)

if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
DPRINTF(sc, ATH_DBG_FATAL,
"unable to update h/w beacon queue parameters\n");
"Unable to update h/w beacon queue parameters\n");
return 0;
} else {
ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
Expand Down Expand Up @@ -132,11 +132,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
avp = (void *)vif->drv_priv;
cabq = sc->beacon.cabq;

if (avp->av_bcbuf == NULL) {
DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n",
avp, avp->av_bcbuf);
if (avp->av_bcbuf == NULL)
return NULL;
}

/* Release the old beacon first */

Expand Down
24 changes: 10 additions & 14 deletions trunk/drivers/net/wireless/ath9k/debug.h
Original file line number Diff line number Diff line change
Expand Up @@ -19,20 +19,16 @@

enum ATH_DEBUG {
ATH_DBG_RESET = 0x00000001,
ATH_DBG_REG_IO = 0x00000002,
ATH_DBG_QUEUE = 0x00000004,
ATH_DBG_EEPROM = 0x00000008,
ATH_DBG_CALIBRATE = 0x00000010,
ATH_DBG_CHANNEL = 0x00000020,
ATH_DBG_INTERRUPT = 0x00000040,
ATH_DBG_REGULATORY = 0x00000080,
ATH_DBG_ANI = 0x00000100,
ATH_DBG_POWER_MGMT = 0x00000200,
ATH_DBG_XMIT = 0x00000400,
ATH_DBG_BEACON = 0x00001000,
ATH_DBG_CONFIG = 0x00002000,
ATH_DBG_KEYCACHE = 0x00004000,
ATH_DBG_FATAL = 0x00008000,
ATH_DBG_QUEUE = 0x00000002,
ATH_DBG_EEPROM = 0x00000004,
ATH_DBG_CALIBRATE = 0x00000008,
ATH_DBG_INTERRUPT = 0x00000010,
ATH_DBG_REGULATORY = 0x00000020,
ATH_DBG_ANI = 0x00000040,
ATH_DBG_XMIT = 0x00000080,
ATH_DBG_BEACON = 0x00000100,
ATH_DBG_CONFIG = 0x00000200,
ATH_DBG_FATAL = 0x00000400,
ATH_DBG_ANY = 0xffffffff
};

Expand Down
24 changes: 12 additions & 12 deletions trunk/drivers/net/wireless/ath9k/eeprom.c
Original file line number Diff line number Diff line change
Expand Up @@ -783,11 +783,11 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
((pdadcValues[4 * j + 3] & 0xFF) << 24);
REG_WRITE(ah, regOffset, reg32);

DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"PDADC (%d,%4x): %4.4x %8.8x\n",
i, regChainOffset, regOffset,
reg32);
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"PDADC: Chain %d | "
"PDADC %3d Value %3d | "
"PDADC %3d Value %3d | "
Expand Down Expand Up @@ -910,15 +910,15 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
ah->eep_ops->get_eeprom_rev(ah) <= 2)
twiceMaxEdgePower = AR5416_MAX_RATE_POWER;

DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
"EXT_ADDITIVE %d\n",
ctlMode, numCtlModes, isHt40CtlMode,
(pCtlMode[ctlMode] & EXT_ADDITIVE));

for (i = 0; (i < AR5416_NUM_CTLS) &&
pEepData->ctlIndex[i]; i++) {
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
"pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
"chan %d\n",
Expand All @@ -941,7 +941,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
IS_CHAN_2GHZ(chan),
AR5416_EEP4K_NUM_BAND_EDGES);

DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" MATCH-EE_IDX %d: ch %d is2 %d "
"2xMinEdge %d chainmask %d chains %d\n",
i, freq, IS_CHAN_2GHZ(chan),
Expand All @@ -961,7 +961,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,

minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);

DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" SEL-Min ctlMode %d pCtlMode %d "
"2xMaxEdge %d sP %d minCtlPwr %d\n",
ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
Expand Down Expand Up @@ -2234,11 +2234,11 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
((pdadcValues[4 * j + 3] & 0xFF) << 24);
REG_WRITE(ah, regOffset, reg32);

DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"PDADC (%d,%4x): %4.4x %8.8x\n",
i, regChainOffset, regOffset,
reg32);
DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"PDADC: Chain %d | PDADC %3d "
"Value %3d | PDADC %3d Value %3d | "
"PDADC %3d Value %3d | PDADC %3d "
Expand Down Expand Up @@ -2415,14 +2415,14 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
ah->eep_ops->get_eeprom_rev(ah) <= 2)
twiceMaxEdgePower = AR5416_MAX_RATE_POWER;

DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
"EXT_ADDITIVE %d\n",
ctlMode, numCtlModes, isHt40CtlMode,
(pCtlMode[ctlMode] & EXT_ADDITIVE));

for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
"pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
"chan %d\n",
Expand All @@ -2441,7 +2441,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);

DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" MATCH-EE_IDX %d: ch %d is2 %d "
"2xMinEdge %d chainmask %d chains %d\n",
i, freq, IS_CHAN_2GHZ(chan),
Expand All @@ -2460,7 +2460,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,

minCtlPower = min(twiceMaxEdgePower, scaledPower);

DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" SEL-Min ctlMode %d pCtlMode %d "
"2xMaxEdge %d sP %d minCtlPwr %d\n",
ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
Expand Down
Loading

0 comments on commit 380c69f

Please sign in to comment.