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yaml
---
r: 334019
b: refs/heads/master
c: 8edc0e6
h: refs/heads/master
i:
  334017: 00f2882
  334015: 5d93992
v: v3
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Hiroaki SHIMODA authored and David S. Miller committed Oct 11, 2012
1 parent 814aac7 commit 39f2fb6
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Showing 3 changed files with 5 additions and 5 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 959859d2fe88fb26e37985445817ef5234bf9a31
refs/heads/master: 8edc0e624db3756783233e464879eb2e3b904c13
6 changes: 3 additions & 3 deletions trunk/drivers/net/ethernet/intel/e1000e/e1000.h
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Expand Up @@ -175,13 +175,13 @@ struct e1000_info;
/*
* in the case of WTHRESH, it appears at least the 82571/2 hardware
* writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
* WTHRESH=4, and since we want 64 bytes at a time written back, set
* it to 5
* WTHRESH=4, so a setting of 5 gives the most efficient bus
* utilization but to avoid possible Tx stalls, set it to 1
*/
#define E1000_TXDCTL_DMA_BURST_ENABLE \
(E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
E1000_TXDCTL_COUNT_DESC | \
(5 << 16) | /* wthresh must be +1 more than desired */\
(1 << 16) | /* wthresh must be +1 more than desired */\
(1 << 8) | /* hthresh */ \
0x1f) /* pthresh */

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2 changes: 1 addition & 1 deletion trunk/drivers/net/ethernet/intel/e1000e/netdev.c
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Expand Up @@ -2831,7 +2831,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
* set up some performance related parameters to encourage the
* hardware to use the bus more efficiently in bursts, depends
* on the tx_int_delay to be enabled,
* wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
* wthresh = 1 ==> burst write is disabled to avoid Tx stalls
* hthresh = 1 ==> prefetch when one or more available
* pthresh = 0x1f ==> prefetch if internal cache 31 or less
* BEWARE: this seems to work but should be considered first if
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