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yaml --- r: 340051 b: refs/heads/master c: 5e505bb h: refs/heads/master i: 340049: ecc70d0 340047: ed4f9d8 v: v3
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Olof Johansson
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--- | ||
refs/heads/master: d1d3b978f67c2c000f9d91387cffa630e738d529 | ||
refs/heads/master: 5e505bb9e7ffcebf02e760425de55d2c52127cef |
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ARM Allwinner SoCs | ||
================== | ||
|
||
This document lists all the ARM Allwinner SoCs that are currently | ||
supported in mainline by the Linux kernel. This document will also | ||
provide links to documentation and or datasheet for these SoCs. | ||
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||
SunXi family | ||
------------ | ||
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Flavors: | ||
Allwinner A10 (sun4i) | ||
Datasheet : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf | ||
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||
Allwinner A13 (sun5i) | ||
Datasheet : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf | ||
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Core: Cortex A8 | ||
Linux kernel mach directory: arch/arm/mach-sunxi |
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Broadcom BCM11351 device tree bindings | ||
------------------------------------------- | ||
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Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140, | ||
bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties: | ||
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Required root node property: | ||
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compatible = "bcm,bcm11351"; |
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Calxeda Highbank Platforms Device Tree Bindings | ||
Calxeda Platforms Device Tree Bindings | ||
----------------------------------------------- | ||
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Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following | ||
properties. | ||
Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the | ||
following properties. | ||
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Required root node properties: | ||
- compatible = "calxeda,highbank"; | ||
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Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following | ||
properties. | ||
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Required root node properties: | ||
- compatible = "calxeda,ecx-2000"; |
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104
trunk/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
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Allwinner Sunxi Interrupt Controller | ||
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Required properties: | ||
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- compatible : should be "allwinner,sunxi-ic" | ||
- reg : Specifies base physical address and size of the registers. | ||
- interrupt-controller : Identifies the node as an interrupt controller | ||
- #interrupt-cells : Specifies the number of cells needed to encode an | ||
interrupt source. The value shall be 1. | ||
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The interrupt sources are as follows: | ||
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0: ENMI | ||
1: UART0 | ||
2: UART1 | ||
3: UART2 | ||
4: UART3 | ||
5: IR0 | ||
6: IR1 | ||
7: I2C0 | ||
8: I2C1 | ||
9: I2C2 | ||
10: SPI0 | ||
11: SPI1 | ||
12: SPI2 | ||
13: SPDIF | ||
14: AC97 | ||
15: TS | ||
16: I2S | ||
17: UART4 | ||
18: UART5 | ||
19: UART6 | ||
20: UART7 | ||
21: KEYPAD | ||
22: TIMER0 | ||
23: TIMER1 | ||
24: TIMER2 | ||
25: TIMER3 | ||
26: CAN | ||
27: DMA | ||
28: PIO | ||
29: TOUCH_PANEL | ||
30: AUDIO_CODEC | ||
31: LRADC | ||
32: SDMC0 | ||
33: SDMC1 | ||
34: SDMC2 | ||
35: SDMC3 | ||
36: MEMSTICK | ||
37: NAND | ||
38: USB0 | ||
39: USB1 | ||
40: USB2 | ||
41: SCR | ||
42: CSI0 | ||
43: CSI1 | ||
44: LCDCTRL0 | ||
45: LCDCTRL1 | ||
46: MP | ||
47: DEFEBE0 | ||
48: DEFEBE1 | ||
49: PMU | ||
50: SPI3 | ||
51: TZASC | ||
52: PATA | ||
53: VE | ||
54: SS | ||
55: EMAC | ||
56: SATA | ||
57: GPS | ||
58: HDMI | ||
59: TVE | ||
60: ACE | ||
61: TVD | ||
62: PS2_0 | ||
63: PS2_1 | ||
64: USB3 | ||
65: USB4 | ||
66: PLE_PFM | ||
67: TIMER4 | ||
68: TIMER5 | ||
69: GPU_GP | ||
70: GPU_GPMMU | ||
71: GPU_PP0 | ||
72: GPU_PPMMU0 | ||
73: GPU_PMU | ||
74: GPU_RSV0 | ||
75: GPU_RSV1 | ||
76: GPU_RSV2 | ||
77: GPU_RSV3 | ||
78: GPU_RSV4 | ||
79: GPU_RSV5 | ||
80: GPU_RSV6 | ||
82: SYNC_TIMER0 | ||
83: SYNC_TIMER1 | ||
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Example: | ||
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intc: interrupt-controller { | ||
compatible = "allwinner,sunxi-ic"; | ||
reg = <0x01c20400 0x400>; | ||
interrupt-controller; | ||
#interrupt-cells = <2>; | ||
}; |
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trunk/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
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Allwinner A1X SoCs Timer Controller | ||
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Required properties: | ||
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- compatible : should be "allwinner,sunxi-timer" | ||
- reg : Specifies base physical address and size of the registers. | ||
- interrupts : The interrupt of the first timer | ||
- clocks: phandle to the source clock (usually a 24 MHz fixed clock) | ||
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Example: | ||
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timer { | ||
compatible = "allwinner,sunxi-timer"; | ||
reg = <0x01c20c00 0x400>; | ||
interrupts = <22>; | ||
clocks = <&osc>; | ||
}; |
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