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Merge tag 'fbdev-4.4' of git://git.kernel.org/pub/scm/linux/kernel/gi…
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…t/tomba/linux

Pull fbdev updates from Tomi Valkeinen:
 - omap: fix hdmi audio configuration issue
 - ssd1307fb: add ssd1309 support
 - tridentfb: support DDC
 - gxt4500: enable support for non-PPC platforms

* tag 'fbdev-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux:
  radeonfb: Deinline large functions
  gxt4500: enable panning
  gxt4500: Use arch_phys_wc_* for framebuffer
  gxt4500: fix color order
  gxt4500: fix 16bpp 565 mode
  gxt4500: enable on non-PPC architectures
  tridentfb: Add DDC support
  fb_ddc: Allow I2C adapters without SCL read capability
  fbdev: ssd1307fb: add ssd1309 support
  fbdev: ssd1307fb: alphabetize headers
  video/omap: remove invalid check
  OMAPDSS: hdmi: Reconfigure and restart audio when display is enabled
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Linus Torvalds committed Nov 10, 2015
2 parents 3e82806 + 08bfb45 commit 3b13866
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Showing 12 changed files with 506 additions and 192 deletions.
3 changes: 2 additions & 1 deletion Documentation/devicetree/bindings/display/ssd1307fb.txt
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Expand Up @@ -2,7 +2,8 @@

Required properties:
- compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
now is i2c, and the supported chips are ssd1305, ssd1306 and ssd1307.
now is i2c, and the supported chips are ssd1305, ssd1306, ssd1307 and
ssd1309.
- reg: Should contain address of the controller on the I2C bus. Most likely
0x3c or 0x3d
- pwm: Should contain the pwm to use according to the OF device tree PWM
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7 changes: 5 additions & 2 deletions drivers/video/fbdev/Kconfig
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Expand Up @@ -1666,6 +1666,8 @@ config FB_TRIDENT
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
select FB_DDC
select FB_MODE_HELPERS
---help---
This is the frame buffer device driver for Trident PCI/AGP chipsets.
Supported chipset families are TGUI 9440/96XX, 3DImage, Blade3D
Expand Down Expand Up @@ -2132,15 +2134,16 @@ config FB_UDL

config FB_IBM_GXT4500
tristate "Framebuffer support for IBM GXT4000P/4500P/6000P/6500P adaptors"
depends on FB && PPC
depends on FB
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Say Y here to enable support for the IBM GXT4000P/6000P and
GXT4500P/6500P display adaptor based on Raster Engine RC1000,
found on some IBM System P (pSeries) machines. This driver
doesn't use Geometry Engine GT1000.
doesn't use Geometry Engine GT1000. This driver also supports
AGP Fire GL2/3/4 cards on x86.

config FB_PS3
tristate "PS3 GPU framebuffer driver"
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133 changes: 131 additions & 2 deletions drivers/video/fbdev/aty/radeon_base.c
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Original file line number Diff line number Diff line change
Expand Up @@ -276,9 +276,138 @@ static int backlight = 1;
static int backlight = 0;
#endif

/*
* prototypes
/* Note about this function: we have some rare cases where we must not schedule,
* this typically happen with our special "wake up early" hook which allows us to
* wake up the graphic chip (and thus get the console back) before everything else
* on some machines that support that mechanism. At this point, interrupts are off
* and scheduling is not permitted
*/
void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
{
if (rinfo->no_schedule || oops_in_progress)
mdelay(ms);
else
msleep(ms);
}

void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo)
{
/* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */
(void)INREG(CLOCK_CNTL_DATA);
(void)INREG(CRTC_GEN_CNTL);
}

void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo)
{
if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
/* we can't deal with posted writes here ... */
_radeon_msleep(rinfo, 5);
}
if (rinfo->errata & CHIP_ERRATA_R300_CG) {
u32 save, tmp;
save = INREG(CLOCK_CNTL_INDEX);
tmp = save & ~(0x3f | PLL_WR_EN);
OUTREG(CLOCK_CNTL_INDEX, tmp);
tmp = INREG(CLOCK_CNTL_DATA);
OUTREG(CLOCK_CNTL_INDEX, save);
}
}

void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask)
{
unsigned long flags;
unsigned int tmp;

spin_lock_irqsave(&rinfo->reg_lock, flags);
tmp = INREG(addr);
tmp &= (mask);
tmp |= (val);
OUTREG(addr, tmp);
spin_unlock_irqrestore(&rinfo->reg_lock, flags);
}

u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
{
u32 data;

OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
radeon_pll_errata_after_index(rinfo);
data = INREG(CLOCK_CNTL_DATA);
radeon_pll_errata_after_data(rinfo);
return data;
}

void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
{
OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
radeon_pll_errata_after_index(rinfo);
OUTREG(CLOCK_CNTL_DATA, val);
radeon_pll_errata_after_data(rinfo);
}

void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
u32 val, u32 mask)
{
unsigned int tmp;

tmp = __INPLL(rinfo, index);
tmp &= (mask);
tmp |= (val);
__OUTPLL(rinfo, index, tmp);
}

void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
int i;

for (i=0; i<2000000; i++) {
if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
return;
udelay(1);
}
printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
}

void radeon_engine_flush(struct radeonfb_info *rinfo)
{
int i;

/* Initiate flush */
OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
~RB2D_DC_FLUSH_ALL);

/* Ensure FIFO is empty, ie, make sure the flush commands
* has reached the cache
*/
_radeon_fifo_wait(rinfo, 64);

/* Wait for the flush to complete */
for (i=0; i < 2000000; i++) {
if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
return;
udelay(1);
}
printk(KERN_ERR "radeonfb: Flush Timeout !\n");
}

void _radeon_engine_idle(struct radeonfb_info *rinfo)
{
int i;

/* ensure FIFO is empty before waiting for idle */
_radeon_fifo_wait(rinfo, 64);

for (i=0; i<2000000; i++) {
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
radeon_engine_flush(rinfo);
return;
}
udelay(1);
}
printk(KERN_ERR "radeonfb: Idle Timeout !\n");
}



static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
{
Expand Down
144 changes: 15 additions & 129 deletions drivers/video/fbdev/aty/radeonfb.h
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Original file line number Diff line number Diff line change
Expand Up @@ -370,20 +370,7 @@ struct radeonfb_info {
* IO macros
*/

/* Note about this function: we have some rare cases where we must not schedule,
* this typically happen with our special "wake up early" hook which allows us to
* wake up the graphic chip (and thus get the console back) before everything else
* on some machines that support that mechanism. At this point, interrupts are off
* and scheduling is not permitted
*/
static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
{
if (rinfo->no_schedule || oops_in_progress)
mdelay(ms);
else
msleep(ms);
}

void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms);

#define INREG8(addr) readb((rinfo->mmio_base)+addr)
#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
Expand All @@ -392,19 +379,7 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
#define INREG(addr) readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)

static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
u32 val, u32 mask)
{
unsigned long flags;
unsigned int tmp;

spin_lock_irqsave(&rinfo->reg_lock, flags);
tmp = INREG(addr);
tmp &= (mask);
tmp |= (val);
OUTREG(addr, tmp);
spin_unlock_irqrestore(&rinfo->reg_lock, flags);
}
void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask);

#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)

Expand All @@ -425,64 +400,24 @@ static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
* possible exception to this rule is the call to unblank(), which may
* be done at irq time if an oops is in progress.
*/
void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo);
static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
{
if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
return;

(void)INREG(CLOCK_CNTL_DATA);
(void)INREG(CRTC_GEN_CNTL);
if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)
radeon_pll_errata_after_index_slow(rinfo);
}

void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo);
static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
{
if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
/* we can't deal with posted writes here ... */
_radeon_msleep(rinfo, 5);
}
if (rinfo->errata & CHIP_ERRATA_R300_CG) {
u32 save, tmp;
save = INREG(CLOCK_CNTL_INDEX);
tmp = save & ~(0x3f | PLL_WR_EN);
OUTREG(CLOCK_CNTL_INDEX, tmp);
tmp = INREG(CLOCK_CNTL_DATA);
OUTREG(CLOCK_CNTL_INDEX, save);
}
}

static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
{
u32 data;

OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
radeon_pll_errata_after_index(rinfo);
data = INREG(CLOCK_CNTL_DATA);
radeon_pll_errata_after_data(rinfo);
return data;
}

static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
u32 val)
{

OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
radeon_pll_errata_after_index(rinfo);
OUTREG(CLOCK_CNTL_DATA, val);
radeon_pll_errata_after_data(rinfo);
}


static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
u32 val, u32 mask)
{
unsigned int tmp;

tmp = __INPLL(rinfo, index);
tmp &= (mask);
tmp |= (val);
__OUTPLL(rinfo, index, tmp);
if (rinfo->errata & (CHIP_ERRATA_PLL_DELAY|CHIP_ERRATA_R300_CG))
radeon_pll_errata_after_data_slow(rinfo);
}

u32 __INPLL(struct radeonfb_info *rinfo, u32 addr);
void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val);
void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
u32 val, u32 mask);

#define INPLL(addr) __INPLL(rinfo, addr)
#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
Expand Down Expand Up @@ -532,58 +467,9 @@ static inline u32 radeon_get_dstbpp(u16 depth)
* 2D Engine helper routines
*/

static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
int i;

for (i=0; i<2000000; i++) {
if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
return;
udelay(1);
}
printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
}

static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
{
int i;

/* Initiate flush */
OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
~RB2D_DC_FLUSH_ALL);

/* Ensure FIFO is empty, ie, make sure the flush commands
* has reached the cache
*/
_radeon_fifo_wait (rinfo, 64);

/* Wait for the flush to complete */
for (i=0; i < 2000000; i++) {
if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
return;
udelay(1);
}
printk(KERN_ERR "radeonfb: Flush Timeout !\n");
}


static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
{
int i;

/* ensure FIFO is empty before waiting for idle */
_radeon_fifo_wait (rinfo, 64);

for (i=0; i<2000000; i++) {
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
radeon_engine_flush (rinfo);
return;
}
udelay(1);
}
printk(KERN_ERR "radeonfb: Idle Timeout !\n");
}

void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries);
void radeon_engine_flush(struct radeonfb_info *rinfo);
void _radeon_engine_idle(struct radeonfb_info *rinfo);

#define radeon_engine_idle() _radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
Expand Down
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