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da8xx-fb: cleanup LCDC configurations
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Configure below LCDC configurations to optimal values, also have an
option configure these optional parameters for platform.
1) AC bias configuration: Required only for passive panels
2) Dma_burst_size:
3) FIFO_DMA_DELAY:
4) FIFO threshold: Does not apply for da830 LCDC.

Patch is verified for 16bpp and 24bpp configurations on da830, da850 and
am335x EVMs.

Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Manjunathappa, Prakash authored and Tomi Valkeinen committed Nov 27, 2012
1 parent f772fab commit 3b43ad2
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Showing 3 changed files with 19 additions and 68 deletions.
22 changes: 1 addition & 21 deletions arch/arm/mach-davinci/devices-da8xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -518,29 +518,9 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
}
}

static const struct display_panel disp_panel = {
QVGA,
16,
16,
COLOR_ACTIVE,
};

static struct lcd_ctrl_config lcd_cfg = {
&disp_panel,
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.panel_shade = COLOR_ACTIVE,
.bpp = 16,
.fdd = 255,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
.fifo_th = 6,
};

struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
Expand Down
43 changes: 17 additions & 26 deletions drivers/video/da8xx-fb.c
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Original file line number Diff line number Diff line change
Expand Up @@ -226,7 +226,8 @@ static struct fb_videomode known_lcd_panels[] = {
.lower_margin = 2,
.hsync_len = 0,
.vsync_len = 0,
.sync = FB_SYNC_CLK_INVERT,
.sync = FB_SYNC_CLK_INVERT |
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
},
/* Sharp LK043T1DG01 */
[1] = {
Expand All @@ -240,7 +241,7 @@ static struct fb_videomode known_lcd_panels[] = {
.lower_margin = 2,
.hsync_len = 41,
.vsync_len = 10,
.sync = 0,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.flag = 0,
},
[2] = {
Expand All @@ -255,7 +256,7 @@ static struct fb_videomode known_lcd_panels[] = {
.lower_margin = 10,
.hsync_len = 10,
.vsync_len = 10,
.sync = 0,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.flag = 0,
},
};
Expand Down Expand Up @@ -387,10 +388,9 @@ static int lcd_cfg_dma(int burst_size, int fifo_th)
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
break;
case 16:
default:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
break;
default:
return -EINVAL;
}

reg |= (fifo_th << 8);
Expand Down Expand Up @@ -435,7 +435,8 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
}

static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
struct fb_videomode *panel)
{
u32 reg;
u32 reg_int;
Expand All @@ -444,7 +445,7 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
LCD_MONO_8BIT_MODE |
LCD_MONOCHROME_MODE);

switch (cfg->p_disp_panel->panel_shade) {
switch (cfg->panel_shade) {
case MONOCHROME:
reg |= LCD_MONOCHROME_MODE;
if (cfg->mono_8bit_mode)
Expand All @@ -457,7 +458,9 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
break;

case COLOR_PASSIVE:
if (cfg->stn_565_mode)
/* AC bias applicable only for Pasive panels */
lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
if (cfg->bpp == 12 && cfg->stn_565_mode)
reg |= LCD_STN_565_ENABLE;
break;

Expand All @@ -478,22 +481,19 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)

reg = lcdc_read(LCD_RASTER_TIMING_2_REG);

if (cfg->sync_ctrl)
reg |= LCD_SYNC_CTRL;
else
reg &= ~LCD_SYNC_CTRL;
reg |= LCD_SYNC_CTRL;

if (cfg->sync_edge)
reg |= LCD_SYNC_EDGE;
else
reg &= ~LCD_SYNC_EDGE;

if (cfg->invert_line_clock)
if (panel->sync & FB_SYNC_HOR_HIGH_ACT)
reg |= LCD_INVERT_LINE_CLOCK;
else
reg &= ~LCD_INVERT_LINE_CLOCK;

if (cfg->invert_frm_clock)
if (panel->sync & FB_SYNC_VERT_HIGH_ACT)
reg |= LCD_INVERT_FRAME_CLOCK;
else
reg &= ~LCD_INVERT_FRAME_CLOCK;
Expand Down Expand Up @@ -738,28 +738,19 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
if (ret < 0)
return ret;

/* Configure the AC bias properties. */
lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);

/* Configure the vertical and horizontal sync properties. */
lcd_cfg_vertical_sync(panel->lower_margin, panel->vsync_len,
panel->upper_margin);
lcd_cfg_horizontal_sync(panel->right_margin, panel->hsync_len,
panel->left_margin);

/* Configure for disply */
ret = lcd_cfg_display(cfg);
ret = lcd_cfg_display(cfg, panel);
if (ret < 0)
return ret;

if (QVGA != cfg->p_disp_panel->panel_type)
return -EINVAL;
bpp = cfg->bpp;

if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
cfg->bpp >= cfg->p_disp_panel->min_bpp)
bpp = cfg->bpp;
else
bpp = cfg->p_disp_panel->max_bpp;
if (bpp == 12)
bpp = 16;
ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
Expand Down Expand Up @@ -1381,7 +1372,7 @@ static int __devinit fb_probe(struct platform_device *device)
da8xx_fb_var.yres_virtual = lcdc_info->yres * LCD_NUM_BUFFERS;

da8xx_fb_var.grayscale =
lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;

da8xx_fb_var.hsync_len = lcdc_info->hsync_len;
Expand Down
22 changes: 1 addition & 21 deletions include/video/da8xx-fb.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,6 @@
#ifndef DA8XX_FB_H
#define DA8XX_FB_H

enum panel_type {
QVGA = 0
};

enum panel_shade {
MONOCHROME = 0,
COLOR_ACTIVE,
Expand All @@ -27,13 +23,6 @@ enum raster_load_mode {
LOAD_PALETTE,
};

struct display_panel {
enum panel_type panel_type; /* QVGA */
int max_bpp;
int min_bpp;
enum panel_shade panel_shade;
};

struct da8xx_lcdc_platform_data {
const char manu_name[10];
void *controller_data;
Expand All @@ -42,7 +31,7 @@ struct da8xx_lcdc_platform_data {
};

struct lcd_ctrl_config {
const struct display_panel *p_disp_panel;
enum panel_shade panel_shade;

/* AC Bias Pin Frequency */
int ac_bias;
Expand All @@ -68,18 +57,9 @@ struct lcd_ctrl_config {
/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
unsigned char mono_8bit_mode;

/* Invert line clock */
unsigned char invert_line_clock;

/* Invert frame clock */
unsigned char invert_frm_clock;

/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
unsigned char sync_edge;

/* Horizontal and Vertical Sync: Control: 0=ignore */
unsigned char sync_ctrl;

/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
unsigned char raster_order;

Expand Down

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