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yaml
---
r: 179778
b: refs/heads/master
c: b2d9591
h: refs/heads/master
v: v3
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Tony Lindgren committed Jan 21, 2010
1 parent 3b52f67 commit 3b44d44
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Showing 17 changed files with 151 additions and 101 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 1daa8c1d75876f690ed8d3f13c806034af5984eb
refs/heads/master: b2d959173fea3e04229b2ff33473b5a031669f66
6 changes: 3 additions & 3 deletions trunk/arch/arm/mach-omap1/clock.c
Original file line number Diff line number Diff line change
Expand Up @@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
struct mpu_rate * ptr;
unsigned long dpll1_rate, ref_rate;

dpll1_rate = clk_get_rate(ck_dpll1_p);
ref_rate = clk_get_rate(ck_ref_p);
dpll1_rate = ck_dpll1_p->rate;
ref_rate = ck_ref_p->rate;

for (ptr = omap1_rate_table; ptr->rate; ptr++) {
if (ptr->xtal != ref_rate)
Expand Down Expand Up @@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
long highest_rate;
unsigned long ref_rate;

ref_rate = clk_get_rate(ck_ref_p);
ref_rate = ck_ref_p->rate;

highest_rate = -EINVAL;

Expand Down
4 changes: 0 additions & 4 deletions trunk/arch/arm/mach-omap2/clock34xx_data.c
Original file line number Diff line number Diff line change
Expand Up @@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
.name = "dpll4_m3x2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m3_ck,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
.flags = INVERT_ENABLE,
Expand Down Expand Up @@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
.name = "dpll4_m6x2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m6_ck,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
.flags = INVERT_ENABLE,
Expand Down Expand Up @@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
.name = "iva2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll2_m2_ck,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.clkdm_name = "iva2_clkdm",
Expand Down Expand Up @@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &l3_ick,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
.recalc = &followparent_recalc,
Expand Down
62 changes: 31 additions & 31 deletions trunk/arch/arm/mach-omap2/clock44xx_data.c
Original file line number Diff line number Diff line change
Expand Up @@ -346,37 +346,37 @@ static struct clk aess_fclk = {
};

static const struct clksel_rate div31_1to31_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
{ .div = 3, .val = 2, .flags = RATE_IN_4430 },
{ .div = 4, .val = 3, .flags = RATE_IN_4430 },
{ .div = 5, .val = 4, .flags = RATE_IN_4430 },
{ .div = 6, .val = 5, .flags = RATE_IN_4430 },
{ .div = 7, .val = 6, .flags = RATE_IN_4430 },
{ .div = 8, .val = 7, .flags = RATE_IN_4430 },
{ .div = 9, .val = 8, .flags = RATE_IN_4430 },
{ .div = 10, .val = 9, .flags = RATE_IN_4430 },
{ .div = 11, .val = 10, .flags = RATE_IN_4430 },
{ .div = 12, .val = 11, .flags = RATE_IN_4430 },
{ .div = 13, .val = 12, .flags = RATE_IN_4430 },
{ .div = 14, .val = 13, .flags = RATE_IN_4430 },
{ .div = 15, .val = 14, .flags = RATE_IN_4430 },
{ .div = 16, .val = 15, .flags = RATE_IN_4430 },
{ .div = 17, .val = 16, .flags = RATE_IN_4430 },
{ .div = 18, .val = 17, .flags = RATE_IN_4430 },
{ .div = 19, .val = 18, .flags = RATE_IN_4430 },
{ .div = 20, .val = 19, .flags = RATE_IN_4430 },
{ .div = 21, .val = 20, .flags = RATE_IN_4430 },
{ .div = 22, .val = 21, .flags = RATE_IN_4430 },
{ .div = 23, .val = 22, .flags = RATE_IN_4430 },
{ .div = 24, .val = 23, .flags = RATE_IN_4430 },
{ .div = 25, .val = 24, .flags = RATE_IN_4430 },
{ .div = 26, .val = 25, .flags = RATE_IN_4430 },
{ .div = 27, .val = 26, .flags = RATE_IN_4430 },
{ .div = 28, .val = 27, .flags = RATE_IN_4430 },
{ .div = 29, .val = 28, .flags = RATE_IN_4430 },
{ .div = 30, .val = 29, .flags = RATE_IN_4430 },
{ .div = 31, .val = 30, .flags = RATE_IN_4430 },
{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
{ .div = 2, .val = 2, .flags = RATE_IN_4430 },
{ .div = 3, .val = 3, .flags = RATE_IN_4430 },
{ .div = 4, .val = 4, .flags = RATE_IN_4430 },
{ .div = 5, .val = 5, .flags = RATE_IN_4430 },
{ .div = 6, .val = 6, .flags = RATE_IN_4430 },
{ .div = 7, .val = 7, .flags = RATE_IN_4430 },
{ .div = 8, .val = 8, .flags = RATE_IN_4430 },
{ .div = 9, .val = 9, .flags = RATE_IN_4430 },
{ .div = 10, .val = 10, .flags = RATE_IN_4430 },
{ .div = 11, .val = 11, .flags = RATE_IN_4430 },
{ .div = 12, .val = 12, .flags = RATE_IN_4430 },
{ .div = 13, .val = 13, .flags = RATE_IN_4430 },
{ .div = 14, .val = 14, .flags = RATE_IN_4430 },
{ .div = 15, .val = 15, .flags = RATE_IN_4430 },
{ .div = 16, .val = 16, .flags = RATE_IN_4430 },
{ .div = 17, .val = 17, .flags = RATE_IN_4430 },
{ .div = 18, .val = 18, .flags = RATE_IN_4430 },
{ .div = 19, .val = 19, .flags = RATE_IN_4430 },
{ .div = 20, .val = 20, .flags = RATE_IN_4430 },
{ .div = 21, .val = 21, .flags = RATE_IN_4430 },
{ .div = 22, .val = 22, .flags = RATE_IN_4430 },
{ .div = 23, .val = 23, .flags = RATE_IN_4430 },
{ .div = 24, .val = 24, .flags = RATE_IN_4430 },
{ .div = 25, .val = 25, .flags = RATE_IN_4430 },
{ .div = 26, .val = 26, .flags = RATE_IN_4430 },
{ .div = 27, .val = 27, .flags = RATE_IN_4430 },
{ .div = 28, .val = 28, .flags = RATE_IN_4430 },
{ .div = 29, .val = 29, .flags = RATE_IN_4430 },
{ .div = 30, .val = 30, .flags = RATE_IN_4430 },
{ .div = 31, .val = 31, .flags = RATE_IN_4430 },
{ .div = 0 },
};

Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/arm/mach-omap2/cpuidle34xx.c
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
local_irq_enable();
local_fiq_enable();

return (u32)timespec_to_ns(&ts_idle)/1000;
return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
}

/**
Expand Down
18 changes: 18 additions & 0 deletions trunk/arch/arm/mach-omap2/irq.c
Original file line number Diff line number Diff line change
Expand Up @@ -274,4 +274,22 @@ void omap_intc_restore_context(void)
}
/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_suspend(void)
{
/* A pending interrupt would prevent OMAP from entering suspend */
omap_ack_irq(0);
}

void omap3_intc_prepare_idle(void)
{
/* Disable autoidle as it can stall interrupt controller */
intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
/* Re-enable autoidle */
intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}
#endif /* CONFIG_ARCH_OMAP3 */
3 changes: 2 additions & 1 deletion trunk/arch/arm/mach-omap2/omap_hwmod.c
Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,8 @@ static int _update_sysc_cache(struct omap_hwmod *oh)

oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);

oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))
oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;

return 0;
}
Expand Down
12 changes: 6 additions & 6 deletions trunk/arch/arm/mach-omap2/pm-debug.c
Original file line number Diff line number Diff line change
Expand Up @@ -54,8 +54,6 @@ int omap2_pm_debug;
regs[reg_count++].val = \
__raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))

static int __init pm_dbg_init(void);

void omap2_pm_dump(int mode, int resume, unsigned int us)
{
struct reg {
Expand Down Expand Up @@ -167,6 +165,8 @@ struct dentry *pm_dbg_dir;

static int pm_dbg_init_done;

static int __init pm_dbg_init(void);

enum {
DEBUG_FILE_COUNTERS = 0,
DEBUG_FILE_TIMERS,
Expand Down Expand Up @@ -488,9 +488,11 @@ int pm_dbg_regset_init(int reg_set)

static int pwrdm_suspend_get(void *data, u64 *val)
{
*val = omap3_pm_get_suspend_state((struct powerdomain *)data);
int ret;
ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
*val = ret;

if (*val >= 0)
if (ret >= 0)
return 0;
return *val;
}
Expand Down Expand Up @@ -604,6 +606,4 @@ static int __init pm_dbg_init(void)
}
arch_initcall(pm_dbg_init);

#else
void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
#endif
8 changes: 6 additions & 2 deletions trunk/arch/arm/mach-omap2/pm.h
Original file line number Diff line number Diff line change
Expand Up @@ -32,12 +32,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
#ifdef CONFIG_PM_DEBUG
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern int omap2_pm_debug;
#else
#define omap2_pm_dump(mode, resume, us) do {} while (0);
#define omap2_pm_debug 0
#endif

#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
extern int pm_dbg_regset_save(int reg_set);
extern int pm_dbg_regset_init(int reg_set);
#else
#define omap2_pm_dump(mode, resume, us) do {} while (0);
#define omap2_pm_debug 0
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
#define pm_dbg_regset_save(reg_set) do {} while (0);
#define pm_dbg_regset_init(reg_set) do {} while (0);
Expand Down
47 changes: 26 additions & 21 deletions trunk/arch/arm/mach-omap2/pm34xx.c
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/delay.h>

#include <plat/sram.h>
#include <plat/clockdomain.h>
Expand Down Expand Up @@ -126,7 +127,15 @@ static void omap3_core_save_context(void)
/* wait for the save to complete */
while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
& PADCONF_SAVE_DONE))
;
udelay(1);

/*
* Force write last pad into memory, as this can fail in some
* cases according to erratas 1.157, 1.185
*/
omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
OMAP343X_CONTROL_MEM_WKUP + 0x2a0);

/* Save the Interrupt controller context */
omap_intc_save_context();
/* Save the GPMC context */
Expand Down Expand Up @@ -392,6 +401,7 @@ void omap_sram_idle(void)
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
omap3_enable_io_chain();
}
omap3_intc_prepare_idle();

/*
* On EMU/HS devices ROM code restores a SRDC value
Expand Down Expand Up @@ -438,6 +448,7 @@ void omap_sram_idle(void)
OMAP3430_GR_MOD,
OMAP3_PRM_VOLTCTRL_OFFSET);
}
omap3_intc_resume_idle();

/* PER */
if (per_next_state < PWRDM_POWER_ON) {
Expand Down Expand Up @@ -578,6 +589,8 @@ static int omap3_pm_suspend(void)
}

omap_uart_prepare_suspend();
omap3_intc_suspend();

omap_sram_idle();

restore:
Expand Down Expand Up @@ -835,6 +848,8 @@ static void __init prcm_setup_regs(void)
CM_AUTOIDLE);
}

omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);

/*
* Set all plls to autoidle. This is needed until autoidle is
* enabled by clockfw
Expand Down Expand Up @@ -875,15 +890,23 @@ static void __init prcm_setup_regs(void)
prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);

/* Enable PM_WKEN to support DSS LPR */
prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
OMAP3430_DSS_MOD, PM_WKEN);

/* Enable wakeups in PER */
prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
OMAP3430_EN_MCBSP4,
OMAP3430_PER_MOD, PM_WKEN);
/* and allow them to wake up MPU */
prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
OMAP3430_EN_MCBSP4,
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);

/* Don't attach IVA interrupts */
Expand All @@ -904,24 +927,6 @@ static void __init prcm_setup_regs(void)
/* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

/* Don't attach IVA interrupts */
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);

/* Clear any pending 'reset' flags */
prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);

/* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

omap3_iva_idle();
omap3_d2d_idle();
}
Expand Down
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