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yaml
---
r: 37496
b: refs/heads/master
c: b9b603d
h: refs/heads/master
v: v3
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Michel Dänzer authored and Dave Airlie committed Sep 21, 2006
1 parent 084bb4c commit 3b82872
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Showing 3 changed files with 13 additions and 8 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: ae1b1a4816ac11075d338af79a239f4c326d675c
refs/heads/master: b9b603dd1c99a68e65ad51cda25379441df2e17b
10 changes: 5 additions & 5 deletions trunk/drivers/char/drm/radeon_cp.c
Original file line number Diff line number Diff line change
Expand Up @@ -864,13 +864,13 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)

dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;

tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
tmp |= RADEON_RB2D_DC_FLUSH_ALL;
RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
tmp |= RADEON_RB3D_DC_FLUSH_ALL;
RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);

for (i = 0; i < dev_priv->usec_timeout; i++) {
if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
& RADEON_RB2D_DC_BUSY)) {
if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
& RADEON_RB3D_DC_BUSY)) {
return 0;
}
DRM_UDELAY(1);
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9 changes: 7 additions & 2 deletions trunk/drivers/char/drm/radeon_drv.h
Original file line number Diff line number Diff line change
Expand Up @@ -545,6 +545,11 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
# define RADEON_RB3D_ZC_FREE (1 << 2)
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
# define RADEON_RB3D_ZC_BUSY (1 << 31)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31)
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
Expand Down Expand Up @@ -987,12 +992,12 @@ do { \
} while (0)

#define RADEON_FLUSH_CACHE() do { \
OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
OUT_RING( RADEON_RB2D_DC_FLUSH ); \
} while (0)

#define RADEON_PURGE_CACHE() do { \
OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
} while (0)

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