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yaml
---
r: 66185
b: refs/heads/master
c: 9b9ea22
h: refs/heads/master
i:
  66183: 8e37945
v: v3
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Ralf Baechle committed Oct 11, 2007
1 parent 536cc10 commit 3c05e76
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Showing 2 changed files with 161 additions and 22 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: d865bea4dace1d42995a6cf552bc4863842623f4
refs/heads/master: 9b9ea2202f3396790f635c62f7498ad75f08f62c
181 changes: 160 additions & 21 deletions trunk/arch/mips/sibyte/sb1250/time.c
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Expand Up @@ -25,6 +25,7 @@
* code to do general bookkeeping (e.g. update jiffies, run
* bottom halves, etc.)
*/
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
Expand Down Expand Up @@ -71,41 +72,170 @@ void __init sb1250_hpt_setup(void)
}
}

/*
* The general purpose timer ticks at 1 Mhz independent if
* the rest of the system
*/
static void sibyte_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned int cpu = smp_processor_id();
void __iomem *timer_cfg, *timer_init;

timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

switch(mode) {
case CLOCK_EVT_MODE_PERIODIC:
__raw_writeq(0, timer_cfg);
__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
timer_cfg);
break;

case CLOCK_EVT_MODE_ONESHOT:
/* Stop the timer until we actually program a shot */
case CLOCK_EVT_MODE_SHUTDOWN:
__raw_writeq(0, timer_cfg);
break;

void sb1250_time_init(void)
case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
;
}
}

static int
sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
{
int cpu = smp_processor_id();
int irq = K_INT_TIMER_0+cpu;
unsigned int cpu = smp_processor_id();
void __iomem *timer_cfg, *timer_init;

/* Only have 4 general purpose timers, and we use last one as hpt */
if (cpu > 2) {
BUG();
timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

__raw_writeq(0, timer_cfg);
__raw_writeq(delta, timer_init);
__raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);

return 0;
}

struct clock_event_device sibyte_hpt_clockevent = {
.name = "sb1250-counter",
.features = CLOCK_EVT_FEAT_PERIODIC,
.set_mode = sibyte_set_mode,
.set_next_event = sibyte_next_event,
.shift = 32,
.irq = 0,
};

static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
{
struct clock_event_device *cd = &sibyte_hpt_clockevent;

cd->event_handler(cd);

return IRQ_HANDLED;
}

static struct irqaction sibyte_irqaction = {
.handler = sibyte_counter_handler,
.flags = IRQF_DISABLED | IRQF_PERCPU,
.name = "timer",
};

/*
* The general purpose timer ticks at 1 Mhz independent if
* the rest of the system
*/
static void sibyte_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned int cpu = smp_processor_id();
void __iomem *timer_cfg, *timer_init;

timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
__raw_writeq(0, timer_cfg);
__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
timer_cfg);
break;

case CLOCK_EVT_MODE_ONESHOT:
/* Stop the timer until we actually program a shot */
case CLOCK_EVT_MODE_SHUTDOWN:
__raw_writeq(0, timer_cfg);
break;

case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
;
}
}

static int
sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
{
unsigned int cpu = smp_processor_id();
void __iomem *timer_cfg, *timer_init;

timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

__raw_writeq(0, timer_cfg);
__raw_writeq(delta, timer_init);
__raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);

return 0;
}

struct clock_event_device sibyte_hpt_clockevent = {
.name = "sb1250-counter",
.features = CLOCK_EVT_FEAT_PERIODIC,
.set_mode = sibyte_set_mode,
.set_next_event = sibyte_next_event,
.shift = 32,
.irq = 0,
};

static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
{
struct clock_event_device *cd = &sibyte_hpt_clockevent;

cd->event_handler(cd);

return IRQ_HANDLED;
}

static struct irqaction sibyte_irqaction = {
.handler = sibyte_counter_handler,
.flags = IRQF_DISABLED | IRQF_PERCPU,
.name = "timer",
};

static void __init sb1250_clockevent_init(void)
{
struct clock_event_device *cd = &sibyte_hpt_clockevent;
unsigned int cpu = smp_processor_id();
int irq = K_INT_TIMER_0 + cpu;

/* Only have 4 general purpose timers, and we use last one as hpt */
BUG_ON(cpu > 2);

sb1250_mask_irq(cpu, irq);

/* Map the timer interrupt to ip[4] of this cpu */
__raw_writeq(IMR_IP4_VAL,
IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
(irq << 3)));

/* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
/* Disable the timer and set up the count */
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
#ifdef CONFIG_SIMULATION
__raw_writeq((50000 / HZ) - 1,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#else
__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#endif

/* Set the timer running */
__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
cd->cpumask = cpumask_of_cpu(0);

sb1250_unmask_irq(cpu, irq);
sb1250_steal_irq(irq);

/*
* This interrupt is "special" in that it doesn't use the request_irq
* way to hook the irq line. The timer interrupt is initialized early
Expand All @@ -114,6 +244,15 @@ void sb1250_time_init(void)
* called directly from irq_handler.S when IP[4] is set during an
* interrupt
*/
setup_irq(irq, &sibyte_irqaction);

clockevents_register_device(cd);
}

void __init plat_time_init(void)
{
sb1250_clocksource_init();
sb1250_clockevent_init();
}

/*
Expand Down

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