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drm/i915: Always use INTEL_INFO() to access the device_info structure
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If we make sure that all the dev_priv->info usages are wrapped by
INTEL_INFO(), we can easily modify the ->info field to be structure and
not a pointer while keeping the const protection in the INTEL_INFO()
macro.

v2: Rebased onto latest drm-nightly

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau authored and Daniel Vetter committed Feb 12, 2014
1 parent e927ecd commit 3d13ef2
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Showing 4 changed files with 29 additions and 20 deletions.
5 changes: 3 additions & 2 deletions drivers/gpu/drm/i915/i915_gem.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1014,7 +1014,8 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
struct timespec *timeout,
struct drm_i915_file_private *file_priv)
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
const bool irq_test_in_progress =
ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
struct timespec before, now;
Expand All @@ -1029,7 +1030,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,

timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;

if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {
if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
gen6_rps_boost(dev_priv);
if (file_priv)
mod_delayed_work(dev_priv->wq,
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/i915/i915_irq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2276,7 +2276,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
PIPE_VBLANK_INTERRUPT_ENABLE);

/* maintain vblank delivery even in deep C-states */
if (dev_priv->info->gen == 3)
if (INTEL_INFO(dev)->gen == 3)
I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

Expand Down Expand Up @@ -2341,7 +2341,7 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe)
unsigned long irqflags;

spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
if (dev_priv->info->gen == 3)
if (INTEL_INFO(dev)->gen == 3)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));

i915_disable_pipestat(dev_priv, pipe,
Expand Down
27 changes: 15 additions & 12 deletions drivers/gpu/drm/i915/intel_display.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1030,7 +1030,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
u32 val;

/* ILK FDI PLL is always enabled */
if (dev_priv->info->gen == 5)
if (INTEL_INFO(dev_priv->dev)->gen == 5)
return;

/* On Haswell, DDI ports are responsible for the FDI PLL setup */
Expand Down Expand Up @@ -1443,7 +1443,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
assert_pipe_disabled(dev_priv, crtc->pipe);

/* No really, not for ILK+ */
BUG_ON(dev_priv->info->gen >= 5);
BUG_ON(INTEL_INFO(dev)->gen >= 5);

/* PLL is protected by panel, make sure we can write it */
if (IS_MOBILE(dev) && !IS_I830(dev))
Expand Down Expand Up @@ -1549,11 +1549,12 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
*/
static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);

/* PCH PLLs only available on ILK, SNB and IVB */
BUG_ON(dev_priv->info->gen < 5);
BUG_ON(INTEL_INFO(dev)->gen < 5);
if (WARN_ON(pll == NULL))
return;

Expand All @@ -1578,11 +1579,12 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)

static void intel_disable_shared_dpll(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);

/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
BUG_ON(INTEL_INFO(dev)->gen < 5);
if (WARN_ON(pll == NULL))
return;

Expand Down Expand Up @@ -1617,7 +1619,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
uint32_t reg, val, pipeconf_val;

/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
BUG_ON(INTEL_INFO(dev)->gen < 5);

/* Make sure PCH DPLL is enabled */
assert_shared_dpll_enabled(dev_priv,
Expand Down Expand Up @@ -1670,7 +1672,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
u32 val, pipeconf_val;

/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);

/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Expand Down Expand Up @@ -1851,7 +1853,8 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane)
{
u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
struct drm_device *dev = dev_priv->dev;
u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);

I915_WRITE(reg, I915_READ(reg));
POSTING_READ(reg);
Expand Down Expand Up @@ -7577,7 +7580,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,

/* we only need to pin inside GTT if cursor is non-phy */
mutex_lock(&dev->struct_mutex);
if (!dev_priv->info->cursor_needs_physical) {
if (!INTEL_INFO(dev)->cursor_needs_physical) {
unsigned alignment;

if (obj->tiling_mode) {
Expand Down Expand Up @@ -7625,7 +7628,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,

finish:
if (intel_crtc->cursor_bo) {
if (dev_priv->info->cursor_needs_physical) {
if (INTEL_INFO(dev)->cursor_needs_physical) {
if (intel_crtc->cursor_bo != obj)
i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
} else
Expand Down Expand Up @@ -8220,7 +8223,7 @@ void intel_mark_idle(struct drm_device *dev)
intel_decrease_pllclock(crtc);
}

if (dev_priv->info->gen >= 6)
if (INTEL_INFO(dev)->gen >= 6)
gen6_rps_idle(dev->dev_private);
}

Expand Down
13 changes: 9 additions & 4 deletions drivers/gpu/drm/i915/intel_pm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3903,9 +3903,10 @@ static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)

unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
unsigned long val;

if (dev_priv->info->gen != 5)
if (INTEL_INFO(dev)->gen != 5)
return 0;

spin_lock_irq(&mchdev_lock);
Expand Down Expand Up @@ -3934,6 +3935,7 @@ unsigned long i915_mch_val(struct drm_i915_private *dev_priv)

static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
{
struct drm_device *dev = dev_priv->dev;
static const struct v_table {
u16 vd; /* in .1 mil */
u16 vm; /* in .1 mil */
Expand Down Expand Up @@ -4067,7 +4069,7 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
{ 16000, 14875, },
{ 16125, 15000, },
};
if (dev_priv->info->is_mobile)
if (INTEL_INFO(dev)->is_mobile)
return v_table[pxvid].vm;
else
return v_table[pxvid].vd;
Expand Down Expand Up @@ -4110,7 +4112,9 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)

void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{
if (dev_priv->info->gen != 5)
struct drm_device *dev = dev_priv->dev;

if (INTEL_INFO(dev)->gen != 5)
return;

spin_lock_irq(&mchdev_lock);
Expand Down Expand Up @@ -4159,9 +4163,10 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)

unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
unsigned long val;

if (dev_priv->info->gen != 5)
if (INTEL_INFO(dev)->gen != 5)
return 0;

spin_lock_irq(&mchdev_lock);
Expand Down

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