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yaml
---
r: 207177
b: refs/heads/master
c: c6673cb
h: refs/heads/master
i:
  207175: 3257af6
v: v3
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FUJITA Tomonori authored and Chris Metcalf committed Jul 6, 2010
1 parent a055b53 commit 3d20acf
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2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f
refs/heads/master: c6673cb54d191dd42935a61fcb0c452a4753fb23
8 changes: 8 additions & 0 deletions trunk/arch/tile/include/asm/cache.h
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Expand Up @@ -31,6 +31,14 @@
#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)

/*
* TILE-Gx is fully coherents so we don't need to define
* ARCH_KMALLOC_MINALIGN.
*/
#ifndef __tilegx__
#define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES
#endif

/* use the cache line size for the L2, which is where it counts */
#define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
#define SMP_CACHE_BYTES L2_CACHE_BYTES
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