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yaml
---
r: 288720
b: refs/heads/master
c: 88c9a65
h: refs/heads/master
v: v3
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Stephane Eranian authored and Ingo Molnar committed Mar 5, 2012
1 parent c15306a commit 3d93e1b
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Showing 2 changed files with 11 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: c5cc2cd906ea9fe73e3c93f9ad824996faa278cc
refs/heads/master: 88c9a65e13f393fd60d8b9e9c659a34f9e39967d
10 changes: 10 additions & 0 deletions trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
Original file line number Diff line number Diff line change
Expand Up @@ -315,6 +315,16 @@ void intel_pmu_lbr_init_snb(void)
/* atom */
void intel_pmu_lbr_init_atom(void)
{
/*
* only models starting at stepping 10 seems
* to have an operational LBR which can freeze
* on PMU interrupt
*/
if (boot_cpu_data.x86_mask < 10) {
pr_cont("LBR disabled due to erratum");
return;
}

x86_pmu.lbr_nr = 8;
x86_pmu.lbr_tos = MSR_LBR_TOS;
x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
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