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[ARM] omap: create a proper tree of clocks
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Traditionally, we've tracked the parent/child relationships between
clk structures by setting the child's parent member to point at the
upstream clock.  As a result, when decending the tree, we have had
to scan all clocks to find the children.

Avoid this wasteful scanning by keeping a list of the clock's children.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored and Russell King committed Feb 8, 2009
1 parent b5088c0 commit 3f0a820
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Showing 9 changed files with 74 additions and 128 deletions.
3 changes: 3 additions & 0 deletions arch/arm/mach-omap1/clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -782,6 +782,9 @@ int __init omap1_clk_init(void)
/* By default all idlect1 clocks are allowed to idle */
arm_idlect1_mask = ~0;

for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
clk_init_one(c->lk.clk);

cpu_mask = 0;
if (cpu_is_omap16xx())
cpu_mask |= CK_16XX;
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7 changes: 2 additions & 5 deletions arch/arm/mach-omap1/clock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -155,16 +155,14 @@ static struct clk ck_dpll1 = {
.name = "ck_dpll1",
.ops = &clkops_null,
.parent = &ck_ref,
.flags = RATE_PROPAGATES,
};

static struct arm_idlect1_clk ck_dpll1out = {
.clk = {
.name = "ck_dpll1out",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL |
ENABLE_REG_32BIT | RATE_PROPAGATES,
.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc,
Expand All @@ -187,7 +185,6 @@ static struct clk arm_ck = {
.name = "arm_ck",
.ops = &clkops_null,
.parent = &ck_dpll1,
.flags = RATE_PROPAGATES,
.rate_offset = CKCTL_ARMDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
Expand Down Expand Up @@ -328,7 +325,7 @@ static struct arm_idlect1_clk tc_ck = {
.name = "tc_ck",
.ops = &clkops_null,
.parent = &ck_dpll1,
.flags = RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
.flags = CLOCK_IDLE_CONTROL,
.rate_offset = CKCTL_TCDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
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4 changes: 2 additions & 2 deletions arch/arm/mach-omap2/clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -175,7 +175,7 @@ void omap2_init_clksel_parent(struct clk *clk)
clk->name, clks->parent->name,
((clk->parent) ?
clk->parent->name : "NULL"));
clk->parent = clks->parent;
clk_reparent(clk, clks->parent);
};
found = 1;
}
Expand Down Expand Up @@ -780,7 +780,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
if (clk->usecount > 0)
_omap2_clk_enable(clk);

clk->parent = new_parent;
clk_reparent(clk, new_parent);

/* CLKSEL clocks follow their parents' rates, divided by a divisor */
clk->rate = new_parent->rate;
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3 changes: 3 additions & 0 deletions arch/arm/mach-omap2/clock24xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -718,6 +718,9 @@ int __init omap2_clk_init(void)
omap2_sys_clk_recalc(&sys_ck);
propagate_rate(&sys_ck);

for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
clk_init_one(c->lk.clk);

cpu_mask = 0;
if (cpu_is_omap2420())
cpu_mask |= CK_242X;
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28 changes: 9 additions & 19 deletions arch/arm/mach-omap2/clock24xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -621,15 +621,14 @@ static struct clk func_32k_ck = {
.name = "func_32k_ck",
.ops = &clkops_null,
.rate = 32000,
.flags = RATE_FIXED | RATE_PROPAGATES,
.flags = RATE_FIXED,
.clkdm_name = "wkup_clkdm",
};

/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
.name = "osc_ck",
.ops = &clkops_oscck,
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_osc_clk_recalc,
};
Expand All @@ -639,7 +638,6 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.name = "sys_ck", /* ~ ref_clk also */
.ops = &clkops_null,
.parent = &osc_ck,
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_sys_clk_recalc,
};
Expand All @@ -648,7 +646,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.name = "alt_ck",
.ops = &clkops_null,
.rate = 54000000,
.flags = RATE_FIXED | RATE_PROPAGATES,
.flags = RATE_FIXED,
.clkdm_name = "wkup_clkdm",
};

Expand Down Expand Up @@ -680,7 +678,6 @@ static struct clk dpll_ck = {
.ops = &clkops_null,
.parent = &sys_ck, /* Can be func_32k also */
.dpll_data = &dpll_dd,
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_dpllcore_recalc,
.set_rate = &omap2_reprogram_dpllcore,
Expand All @@ -691,7 +688,7 @@ static struct clk apll96_ck = {
.ops = &clkops_fixed,
.parent = &sys_ck,
.rate = 96000000,
.flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
.flags = RATE_FIXED | ENABLE_ON_INIT,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
Expand All @@ -702,7 +699,7 @@ static struct clk apll54_ck = {
.ops = &clkops_fixed,
.parent = &sys_ck,
.rate = 54000000,
.flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
.flags = RATE_FIXED | ENABLE_ON_INIT,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
Expand Down Expand Up @@ -734,7 +731,6 @@ static struct clk func_54m_ck = {
.name = "func_54m_ck",
.ops = &clkops_null,
.parent = &apll54_ck, /* can also be alt_clk */
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Expand All @@ -747,7 +743,6 @@ static struct clk core_ck = {
.name = "core_ck",
.ops = &clkops_null,
.parent = &dpll_ck, /* can also be 32k */
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
Expand All @@ -774,7 +769,6 @@ static struct clk func_96m_ck = {
.name = "func_96m_ck",
.ops = &clkops_null,
.parent = &apll96_ck,
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Expand Down Expand Up @@ -807,7 +801,6 @@ static struct clk func_48m_ck = {
.name = "func_48m_ck",
.ops = &clkops_null,
.parent = &apll96_ck, /* 96M or Alt */
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Expand All @@ -823,7 +816,6 @@ static struct clk func_12m_ck = {
.ops = &clkops_null,
.parent = &func_48m_ck,
.fixed_div = 4,
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_fixed_divisor_recalc,
};
Expand Down Expand Up @@ -876,7 +868,6 @@ static struct clk sys_clkout_src = {
.name = "sys_clkout_src",
.ops = &clkops_omap2_dflt,
.parent = &func_54m_ck,
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
Expand Down Expand Up @@ -921,7 +912,6 @@ static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src",
.ops = &clkops_omap2_dflt,
.parent = &func_54m_ck,
.flags = RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
Expand Down Expand Up @@ -992,7 +982,7 @@ static struct clk mpu_ck = { /* Control cpu */
.name = "mpu_ck",
.ops = &clkops_null,
.parent = &core_ck,
.flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
.flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "mpu_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
Expand Down Expand Up @@ -1034,7 +1024,7 @@ static struct clk dsp_fck = {
.name = "dsp_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
.flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
.flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "dsp_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
Expand Down Expand Up @@ -1102,7 +1092,7 @@ static struct clk iva1_ifck = {
.name = "iva1_ifck",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
.flags = CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
.flags = CONFIG_PARTICIPANT | DELAYED_APP,
.clkdm_name = "iva1_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
Expand Down Expand Up @@ -1165,7 +1155,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
.name = "core_l3_ck",
.ops = &clkops_null,
.parent = &core_ck,
.flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
.flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "core_l3_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
Expand Down Expand Up @@ -1227,7 +1217,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
.name = "l4_ck",
.ops = &clkops_null,
.parent = &core_l3_ck,
.flags = DELAYED_APP | RATE_PROPAGATES,
.flags = DELAYED_APP,
.clkdm_name = "core_l4_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
Expand Down
3 changes: 3 additions & 0 deletions arch/arm/mach-omap2/clock34xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -903,6 +903,9 @@ int __init omap2_clk_init(void)

clk_init(&omap2_clk_functions);

for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
clk_init_one(c->lk.clk);

for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
if (c->cpu & cpu_clkflg) {
clkdev_add(&c->lk);
Expand Down
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