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ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain In case of AM33xx family of devices, there is no consistency between PWRSTCTRL & PWRSTST register offsers in PRM space, for example - PRM_XXX PWRSTCTRL PWRSTST ======================================= PRM_PER_MOD: 0x0C, 0x08 PRM_WKUP_MOD: 0x04, 0x08 PRM_MPU_MOD: 0x00, 0x04 PRM_DEVICE_MOD: NA, NA And also, there is no consistency between bit-offsets inside PWRSTCTRL & PWRSTST register, for example - PRM_XXX LOGICRET MEMON MEMRET ======================================= GFX_PWRCTRL: 2, 17, 6 PER_PWRCTRL: 3, 25, 29 MPU_PWRCTRL: 2, 18, 22 WKUP_PWRCTRL: 3, NA, NA This means, we need to maintain and pass on all this information in powerdomain handle; so adding fields for, - PWRSTCTRL/ST register offset - Logic retention state mask - mem_on/ret/pwrst/retst mask Currently, this fields is only applicable and used for AM33XX devices. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: this patch is a combination of "Add offset & mask fields to struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx: Add powerdomain & PRM support"; updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,229 @@ | ||
| /* | ||
| * AM33XX Powerdomain control | ||
| * | ||
| * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| * | ||
| * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak | ||
| * <rnayak@ti.com> | ||
| * | ||
| * This program is free software; you can redistribute it and/or | ||
| * modify it under the terms of the GNU General Public License as | ||
| * published by the Free Software Foundation version 2. | ||
| * | ||
| * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| * kind, whether express or implied; without even the implied warranty | ||
| * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| * GNU General Public License for more details. | ||
| */ | ||
|
|
||
| #include <linux/io.h> | ||
| #include <linux/errno.h> | ||
| #include <linux/delay.h> | ||
|
|
||
| #include <plat/prcm.h> | ||
|
|
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| #include "powerdomain.h" | ||
| #include "prm33xx.h" | ||
| #include "prm-regbits-33xx.h" | ||
|
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|
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| static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | ||
| { | ||
| am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, | ||
| (pwrst << OMAP_POWERSTATE_SHIFT), | ||
| pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| return 0; | ||
| } | ||
|
|
||
| static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | ||
| { | ||
| u32 v; | ||
|
|
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| v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| v &= OMAP_POWERSTATE_MASK; | ||
| v >>= OMAP_POWERSTATE_SHIFT; | ||
|
|
||
| return v; | ||
| } | ||
|
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| static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) | ||
| { | ||
| u32 v; | ||
|
|
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| v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| v &= OMAP_POWERSTATEST_MASK; | ||
| v >>= OMAP_POWERSTATEST_SHIFT; | ||
|
|
||
| return v; | ||
| } | ||
|
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||
| static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | ||
| { | ||
| u32 v; | ||
|
|
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| v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| v &= AM33XX_LASTPOWERSTATEENTERED_MASK; | ||
| v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; | ||
|
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| return v; | ||
| } | ||
|
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| static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | ||
| { | ||
| am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, | ||
| (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), | ||
| pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| return 0; | ||
| } | ||
|
|
||
| static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | ||
| { | ||
| am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, | ||
| AM33XX_LASTPOWERSTATEENTERED_MASK, | ||
| pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| return 0; | ||
| } | ||
|
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||
| static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | ||
| { | ||
| u32 m; | ||
|
|
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| m = pwrdm->logicretstate_mask; | ||
| if (!m) | ||
| return -EINVAL; | ||
|
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| am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
| pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
|
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| return 0; | ||
| } | ||
|
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| static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | ||
| { | ||
| u32 v; | ||
|
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| v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| v &= AM33XX_LOGICSTATEST_MASK; | ||
| v >>= AM33XX_LOGICSTATEST_SHIFT; | ||
|
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| return v; | ||
| } | ||
|
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| static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) | ||
| { | ||
| u32 v, m; | ||
|
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| m = pwrdm->logicretstate_mask; | ||
| if (!m) | ||
| return -EINVAL; | ||
|
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| v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| v &= m; | ||
| v >>= __ffs(m); | ||
|
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| return v; | ||
| } | ||
|
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| static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, | ||
| u8 pwrst) | ||
| { | ||
| u32 m; | ||
|
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| m = pwrdm->mem_on_mask[bank]; | ||
| if (!m) | ||
| return -EINVAL; | ||
|
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| am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
| pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
|
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| return 0; | ||
| } | ||
|
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| static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | ||
| u8 pwrst) | ||
| { | ||
| u32 m; | ||
|
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| m = pwrdm->mem_ret_mask[bank]; | ||
| if (!m) | ||
| return -EINVAL; | ||
|
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| am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
| pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
|
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| return 0; | ||
| } | ||
|
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| static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | ||
| { | ||
| u32 m, v; | ||
|
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| m = pwrdm->mem_pwrst_mask[bank]; | ||
| if (!m) | ||
| return -EINVAL; | ||
|
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| v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| v &= m; | ||
| v >>= __ffs(m); | ||
|
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| return v; | ||
| } | ||
|
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| static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | ||
| { | ||
| u32 m, v; | ||
|
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| m = pwrdm->mem_retst_mask[bank]; | ||
| if (!m) | ||
| return -EINVAL; | ||
|
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| v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| v &= m; | ||
| v >>= __ffs(m); | ||
|
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| return v; | ||
| } | ||
|
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| static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) | ||
| { | ||
| u32 c = 0; | ||
|
|
||
| /* | ||
| * REVISIT: pwrdm_wait_transition() may be better implemented | ||
| * via a callback and a periodic timer check -- how long do we expect | ||
| * powerdomain transitions to take? | ||
| */ | ||
|
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| /* XXX Is this udelay() value meaningful? */ | ||
| while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) | ||
| & OMAP_INTRANSITION_MASK) && | ||
| (c++ < PWRDM_TRANSITION_BAILOUT)) | ||
| udelay(1); | ||
|
|
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| if (c > PWRDM_TRANSITION_BAILOUT) { | ||
| pr_err("powerdomain: %s: waited too long to complete transition\n", | ||
| pwrdm->name); | ||
| return -EAGAIN; | ||
| } | ||
|
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| pr_debug("powerdomain: completed transition in %d loops\n", c); | ||
|
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| return 0; | ||
| } | ||
|
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| struct pwrdm_ops am33xx_pwrdm_operations = { | ||
| .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, | ||
| .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, | ||
| .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, | ||
| .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, | ||
| .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, | ||
| .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, | ||
| .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, | ||
| .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, | ||
| .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, | ||
| .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, | ||
| .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, | ||
| .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, | ||
| .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, | ||
| .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, | ||
| }; |
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