---

yaml --- r: 203348 b: refs/heads/master c: c68cd6c h: refs/heads/master v: v3
git-mirror · Jun 17, 2010 · 404ae6b · 404ae6b
1 parent 058861c
commit 404ae6b
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diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 0a17d8c744e44617a3c22e7af68b4c5c9c1c5dba
+refs/heads/master: c68cd6cc21eb329c47ff020ff7412bf58176984e
diff --git a/trunk/Documentation/networking/README.ipw2200 b/trunk/Documentation/networking/README.ipw2200
@@ -171,7 +171,7 @@ Where the supported parameter are:
 
   led
 	Can be used to turn on experimental LED code.
-	0 = Off, 1 = On.  Default is 1.
+	0 = Off, 1 = On.  Default is 0.
 
   mode
 	Can be used to set the default mode of the adapter.  

diff --git a/trunk/Documentation/networking/caif/spi_porting.txt b/trunk/Documentation/networking/caif/spi_porting.txt
diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS
@@ -2978,14 +2978,20 @@ F:	drivers/net/ixgb/
 F:	drivers/net/ixgbe/
 
 INTEL PRO/WIRELESS 2100 NETWORK CONNECTION SUPPORT
+M:	Reinette Chatre <reinette.chatre@intel.com>
+M:	Intel Linux Wireless <ilw@linux.intel.com>
 L:	linux-wireless@vger.kernel.org
-S:	Orphan
+W:	http://ipw2100.sourceforge.net
+S:	Odd Fixes
 F:	Documentation/networking/README.ipw2100
 F:	drivers/net/wireless/ipw2x00/ipw2100.*
 
 INTEL PRO/WIRELESS 2915ABG NETWORK CONNECTION SUPPORT
+M:	Reinette Chatre <reinette.chatre@intel.com>
+M:	Intel Linux Wireless <ilw@linux.intel.com>
 L:	linux-wireless@vger.kernel.org
-S:	Orphan
+W:	http://ipw2200.sourceforge.net
+S:	Odd Fixes
 F:	Documentation/networking/README.ipw2200
 F:	drivers/net/wireless/ipw2x00/ipw2200.*
 

diff --git a/trunk/arch/microblaze/include/asm/system.h b/trunk/arch/microblaze/include/asm/system.h
@@ -101,7 +101,10 @@ extern struct dentry *of_debugfs_root;
  * MicroBlaze doesn't handle unaligned accesses in hardware.
  *
  * Based on this we force the IP header alignment in network drivers.
+ * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
+ * cacheline alignment of buffers.
  */
 #define NET_IP_ALIGN	2
+#define NET_SKB_PAD	L1_CACHE_BYTES
 
 #endif /* _ASM_MICROBLAZE_SYSTEM_H */
diff --git a/trunk/arch/powerpc/include/asm/system.h b/trunk/arch/powerpc/include/asm/system.h
@@ -515,8 +515,11 @@ __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
  * powers of 2 writes until it reaches sufficient alignment).
  *
  * Based on this we disable the IP header alignment in network drivers.
+ * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
+ * cacheline alignment of buffers.
  */
 #define NET_IP_ALIGN	0
+#define NET_SKB_PAD	L1_CACHE_BYTES
 
 #define cmpxchg64(ptr, o, n)						\
   ({									\

diff --git a/trunk/arch/x86/include/asm/system.h b/trunk/arch/x86/include/asm/system.h
@@ -457,11 +457,4 @@ static inline void rdtsc_barrier(void)
 	alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 }
 
-/*
- * We handle most unaligned accesses in hardware.  On the other hand
- * unaligned DMA can be quite expensive on some Nehalem processors.
- *
- * Based on this we disable the IP header alignment in network drivers.
- */
-#define NET_IP_ALIGN	0
 #endif /* _ASM_X86_SYSTEM_H */