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mtd: nand: ndfc: add multiple chip select support
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This patch extends NDFC driver to support all 4 chip selects
available in NDFC NAND controller. Tested on custom 460EX board
with 2 chip select NAND device.

Artem: white-space cleanups

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Felix Radensky authored and David Woodhouse committed May 25, 2011
1 parent 1ddd0d9 commit 410fe2f
Showing 1 changed file with 35 additions and 17 deletions.
52 changes: 35 additions & 17 deletions drivers/mtd/nand/ndfc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@
#include <linux/of_platform.h>
#include <asm/io.h>

#define NDFC_MAX_CS 4

struct ndfc_controller {
struct platform_device *ofdev;
Expand All @@ -46,12 +47,13 @@ struct ndfc_controller {
#endif
};

static struct ndfc_controller ndfc_ctrl;
static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];

static void ndfc_select_chip(struct mtd_info *mtd, int chip)
{
uint32_t ccr;
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *nchip = mtd->priv;
struct ndfc_controller *ndfc = nchip->priv;

ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
if (chip >= 0) {
Expand All @@ -64,7 +66,8 @@ static void ndfc_select_chip(struct mtd_info *mtd, int chip)

static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *chip = mtd->priv;
struct ndfc_controller *ndfc = chip->priv;

if (cmd == NAND_CMD_NONE)
return;
Expand All @@ -77,15 +80,17 @@ static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)

static int ndfc_ready(struct mtd_info *mtd)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *chip = mtd->priv;
struct ndfc_controller *ndfc = chip->priv;

return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
}

static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
{
uint32_t ccr;
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *chip = mtd->priv;
struct ndfc_controller *ndfc = chip->priv;

ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
ccr |= NDFC_CCR_RESET_ECC;
Expand All @@ -96,7 +101,8 @@ static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
static int ndfc_calculate_ecc(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_code)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *chip = mtd->priv;
struct ndfc_controller *ndfc = chip->priv;
uint32_t ecc;
uint8_t *p = (uint8_t *)&ecc;

Expand All @@ -119,7 +125,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtd,
*/
static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *chip = mtd->priv;
struct ndfc_controller *ndfc = chip->priv;
uint32_t *p = (uint32_t *) buf;

for(;len > 0; len -= 4)
Expand All @@ -128,7 +135,8 @@ static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)

static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *chip = mtd->priv;
struct ndfc_controller *ndfc = chip->priv;
uint32_t *p = (uint32_t *) buf;

for(;len > 0; len -= 4)
Expand All @@ -137,7 +145,8 @@ static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)

static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct nand_chip *chip = mtd->priv;
struct ndfc_controller *ndfc = chip->priv;
uint32_t *p = (uint32_t *) buf;

for(;len > 0; len -= 4)
Expand Down Expand Up @@ -179,6 +188,7 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc,
chip->ecc.mode = NAND_ECC_HW;
chip->ecc.size = 256;
chip->ecc.bytes = 3;
chip->priv = ndfc;

ndfc->mtd.priv = chip;
ndfc->mtd.owner = THIS_MODULE;
Expand Down Expand Up @@ -227,23 +237,31 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc,

static int __devinit ndfc_probe(struct platform_device *ofdev)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
struct ndfc_controller *ndfc;
const __be32 *reg;
u32 ccr;
int err, len;

spin_lock_init(&ndfc->ndfc_control.lock);
init_waitqueue_head(&ndfc->ndfc_control.wq);
ndfc->ofdev = ofdev;
dev_set_drvdata(&ofdev->dev, ndfc);
int err, len, cs;

/* Read the reg property to get the chip select */
reg = of_get_property(ofdev->dev.of_node, "reg", &len);
if (reg == NULL || len != 12) {
dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
return -ENOENT;
}
ndfc->chip_select = be32_to_cpu(reg[0]);

cs = be32_to_cpu(reg[0]);
if (cs >= NDFC_MAX_CS) {
dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
return -EINVAL;
}

ndfc = &ndfc_ctrl[cs];
ndfc->chip_select = cs;

spin_lock_init(&ndfc->ndfc_control.lock);
init_waitqueue_head(&ndfc->ndfc_control.wq);
ndfc->ofdev = ofdev;
dev_set_drvdata(&ofdev->dev, ndfc);

ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
if (!ndfc->ndfcbase) {
Expand Down

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