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yaml
---
r: 288363
b: refs/heads/master
c: d47775c
h: refs/heads/master
i:
  288361: 487aff2
  288359: d9e6cb4
v: v3
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David S. Miller committed Mar 7, 2012
1 parent 1124aa5 commit 4186162
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Showing 67 changed files with 307 additions and 164 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 7f466cff75f16ac545f34c7876e6f80225a36a6d
refs/heads/master: d47775c4a7a40ecd048400cf770504ad1f2cd3df
3 changes: 2 additions & 1 deletion trunk/Documentation/input/alps.txt
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,8 @@ Detection

All ALPS touchpads should respond to the "E6 report" command sequence:
E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
00-00-64.
00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
if some buttons are pressed.

If the E6 report is successful, the touchpad model is identified using the "E7
report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is
Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/arm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -1280,7 +1280,7 @@ config ARM_ERRATA_743622
depends on CPU_V7
help
This option enables the workaround for the 743622 Cortex-A9
(r2p0..r2p2) erratum. Under very rare conditions, a faulty
(r2p*) erratum. Under very rare conditions, a faulty
optimisation in the Cortex-A9 Store Buffer may lead to data
corruption. This workaround sets a specific bit in the diagnostic
register of the Cortex-A9 which disables the Store Buffer
Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/arm/include/asm/pmu.h
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);

u64 armpmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc,
int idx, int overflow);
int idx);

int armpmu_event_set_period(struct perf_event *event,
struct hw_perf_event *hwc,
Expand Down
1 change: 1 addition & 0 deletions trunk/arch/arm/kernel/ecard.c
Original file line number Diff line number Diff line change
Expand Up @@ -242,6 +242,7 @@ static void ecard_init_pgtables(struct mm_struct *mm)

memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE));

vma.vm_flags = VM_EXEC;
vma.vm_mm = mm;

flush_tlb_range(&vma, IO_START, IO_START + IO_SIZE);
Expand Down
45 changes: 34 additions & 11 deletions trunk/arch/arm/kernel/perf_event.c
Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,7 @@ armpmu_event_set_period(struct perf_event *event,
u64
armpmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc,
int idx, int overflow)
int idx)
{
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
u64 delta, prev_raw_count, new_raw_count;
Expand All @@ -193,13 +193,7 @@ armpmu_event_update(struct perf_event *event,
new_raw_count) != prev_raw_count)
goto again;

new_raw_count &= armpmu->max_period;
prev_raw_count &= armpmu->max_period;

if (overflow)
delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
else
delta = new_raw_count - prev_raw_count;
delta = (new_raw_count - prev_raw_count) & armpmu->max_period;

local64_add(delta, &event->count);
local64_sub(delta, &hwc->period_left);
Expand All @@ -216,7 +210,7 @@ armpmu_read(struct perf_event *event)
if (hwc->idx < 0)
return;

armpmu_event_update(event, hwc, hwc->idx, 0);
armpmu_event_update(event, hwc, hwc->idx);
}

static void
Expand All @@ -232,7 +226,7 @@ armpmu_stop(struct perf_event *event, int flags)
if (!(hwc->state & PERF_HES_STOPPED)) {
armpmu->disable(hwc, hwc->idx);
barrier(); /* why? */
armpmu_event_update(event, hwc, hwc->idx, 0);
armpmu_event_update(event, hwc, hwc->idx);
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
}
}
Expand Down Expand Up @@ -518,7 +512,13 @@ __hw_perf_event_init(struct perf_event *event)
hwc->config_base |= (unsigned long)mapping;

if (!hwc->sample_period) {
hwc->sample_period = armpmu->max_period;
/*
* For non-sampling runs, limit the sample_period to half
* of the counter width. That way, the new counter value
* is far less likely to overtake the previous one unless
* you have some serious IRQ latency issues.
*/
hwc->sample_period = armpmu->max_period >> 1;
hwc->last_period = hwc->sample_period;
local64_set(&hwc->period_left, hwc->sample_period);
}
Expand Down Expand Up @@ -679,6 +679,28 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
armpmu->type = ARM_PMU_DEVICE_CPU;
}

/*
* PMU hardware loses all context when a CPU goes offline.
* When a CPU is hotplugged back in, since some hardware registers are
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
* junk values out of them.
*/
static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
unsigned long action, void *hcpu)
{
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
return NOTIFY_DONE;

if (cpu_pmu && cpu_pmu->reset)
cpu_pmu->reset(NULL);

return NOTIFY_OK;
}

static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
.notifier_call = pmu_cpu_notify,
};

/*
* CPU PMU identification and registration.
*/
Expand Down Expand Up @@ -730,6 +752,7 @@ init_hw_perf_events(void)
pr_info("enabled with %s PMU driver, %d counters available\n",
cpu_pmu->name, cpu_pmu->num_events);
cpu_pmu_init(cpu_pmu);
register_cpu_notifier(&pmu_cpu_notifier);
armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
} else {
pr_info("no hardware support available\n");
Expand Down
22 changes: 3 additions & 19 deletions trunk/arch/arm/kernel/perf_event_v6.c
Original file line number Diff line number Diff line change
Expand Up @@ -467,23 +467,6 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}

static int counter_is_active(unsigned long pmcr, int idx)
{
unsigned long mask = 0;
if (idx == ARMV6_CYCLE_COUNTER)
mask = ARMV6_PMCR_CCOUNT_IEN;
else if (idx == ARMV6_COUNTER0)
mask = ARMV6_PMCR_COUNT0_IEN;
else if (idx == ARMV6_COUNTER1)
mask = ARMV6_PMCR_COUNT1_IEN;

if (mask)
return pmcr & mask;

WARN_ONCE(1, "invalid counter number (%d)\n", idx);
return 0;
}

static irqreturn_t
armv6pmu_handle_irq(int irq_num,
void *dev)
Expand Down Expand Up @@ -513,7 +496,8 @@ armv6pmu_handle_irq(int irq_num,
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;

if (!counter_is_active(pmcr, idx))
/* Ignore if we don't have an event. */
if (!event)
continue;

/*
Expand All @@ -524,7 +508,7 @@ armv6pmu_handle_irq(int irq_num,
continue;

hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;
Expand Down
11 changes: 10 additions & 1 deletion trunk/arch/arm/kernel/perf_event_v7.c
Original file line number Diff line number Diff line change
Expand Up @@ -809,6 +809,11 @@ static inline int armv7_pmnc_disable_intens(int idx)

counter = ARMV7_IDX_TO_COUNTER(idx);
asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
isb();
/* Clear the overflow flag in case an interrupt is pending. */
asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));
isb();

return idx;
}

Expand Down Expand Up @@ -955,6 +960,10 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;

/* Ignore if we don't have an event. */
if (!event)
continue;

/*
* We have a single interrupt for all counters. Check that
* each counter has overflowed before we process it.
Expand All @@ -963,7 +972,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
continue;

hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;
Expand Down
20 changes: 16 additions & 4 deletions trunk/arch/arm/kernel/perf_event_xscale.c
Original file line number Diff line number Diff line change
Expand Up @@ -255,11 +255,14 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;

if (!event)
continue;

if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
continue;

hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;
Expand Down Expand Up @@ -592,11 +595,14 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;

if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
if (!event)
continue;

if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx))
continue;

hwc = &event->hw;
armpmu_event_update(event, hwc, idx, 1);
armpmu_event_update(event, hwc, idx);
data.period = event->hw.last_period;
if (!armpmu_event_set_period(event, hwc, idx))
continue;
Expand Down Expand Up @@ -663,7 +669,7 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
static void
xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
{
unsigned long flags, ien, evtsel;
unsigned long flags, ien, evtsel, of_flags;
struct pmu_hw_events *events = cpu_pmu->get_hw_events();

ien = xscale2pmu_read_int_enable();
Expand All @@ -672,26 +678,31 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
switch (idx) {
case XSCALE_CYCLE_COUNTER:
ien &= ~XSCALE2_CCOUNT_INT_EN;
of_flags = XSCALE2_CCOUNT_OVERFLOW;
break;
case XSCALE_COUNTER0:
ien &= ~XSCALE2_COUNT0_INT_EN;
evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
of_flags = XSCALE2_COUNT0_OVERFLOW;
break;
case XSCALE_COUNTER1:
ien &= ~XSCALE2_COUNT1_INT_EN;
evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
of_flags = XSCALE2_COUNT1_OVERFLOW;
break;
case XSCALE_COUNTER2:
ien &= ~XSCALE2_COUNT2_INT_EN;
evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
of_flags = XSCALE2_COUNT2_OVERFLOW;
break;
case XSCALE_COUNTER3:
ien &= ~XSCALE2_COUNT3_INT_EN;
evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
of_flags = XSCALE2_COUNT3_OVERFLOW;
break;
default:
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
Expand All @@ -701,6 +712,7 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
raw_spin_lock_irqsave(&events->pmu_lock, flags);
xscale2pmu_write_event_select(evtsel);
xscale2pmu_write_int_enable(ien);
xscale2pmu_write_overflow_flags(of_flags);
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}

Expand Down
19 changes: 10 additions & 9 deletions trunk/arch/arm/mach-at91/at91sam9g45_devices.c
Original file line number Diff line number Diff line change
Expand Up @@ -38,10 +38,6 @@
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
static u64 hdmac_dmamask = DMA_BIT_MASK(32);

static struct at_dma_platform_data atdma_pdata = {
.nr_channels = 8,
};

static struct resource hdmac_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_DMA,
Expand All @@ -56,22 +52,27 @@ static struct resource hdmac_resources[] = {
};

static struct platform_device at_hdmac_device = {
.name = "at_hdmac",
.name = "at91sam9g45_dma",
.id = -1,
.dev = {
.dma_mask = &hdmac_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &atdma_pdata,
},
.resource = hdmac_resources,
.num_resources = ARRAY_SIZE(hdmac_resources),
};

void __init at91_add_device_hdmac(void)
{
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
platform_device_register(&at_hdmac_device);
#if defined(CONFIG_OF)
struct device_node *of_node =
of_find_node_by_name(NULL, "dma-controller");

if (of_node)
of_node_put(of_node);
else
#endif
platform_device_register(&at_hdmac_device);
}
#else
void __init at91_add_device_hdmac(void) {}
Expand Down
8 changes: 1 addition & 7 deletions trunk/arch/arm/mach-at91/at91sam9rl_devices.c
Original file line number Diff line number Diff line change
Expand Up @@ -33,10 +33,6 @@
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
static u64 hdmac_dmamask = DMA_BIT_MASK(32);

static struct at_dma_platform_data atdma_pdata = {
.nr_channels = 2,
};

static struct resource hdmac_resources[] = {
[0] = {
.start = AT91SAM9RL_BASE_DMA,
Expand All @@ -51,20 +47,18 @@ static struct resource hdmac_resources[] = {
};

static struct platform_device at_hdmac_device = {
.name = "at_hdmac",
.name = "at91sam9rl_dma",
.id = -1,
.dev = {
.dma_mask = &hdmac_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &atdma_pdata,
},
.resource = hdmac_resources,
.num_resources = ARRAY_SIZE(hdmac_resources),
};

void __init at91_add_device_hdmac(void)
{
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
platform_device_register(&at_hdmac_device);
}
#else
Expand Down
2 changes: 2 additions & 0 deletions trunk/arch/arm/mach-ep93xx/vision_ep9307.c
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@
#include <mach/ep93xx_spi.h>
#include <mach/gpio-ep93xx.h>

#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
Expand Down Expand Up @@ -361,6 +362,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
.atag_offset = 0x100,
.map_io = vision_map_io,
.init_irq = ep93xx_init_irq,
.handle_irq = vic_handle_irq,
.timer = &ep93xx_timer,
.init_machine = vision_init_machine,
.restart = ep93xx_restart,
Expand Down
2 changes: 2 additions & 0 deletions trunk/arch/arm/mach-exynos/mach-universal_c210.c
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/mfd/max8998.h>
#include <linux/regulator/machine.h>
Expand Down Expand Up @@ -595,6 +596,7 @@ static struct mxt_platform_data qt602240_platform_data = {
.threshold = 0x28,
.voltage = 2800000, /* 2.8V */
.orient = MXT_DIAGONAL,
.irqflags = IRQF_TRIGGER_FALLING,
};

static struct i2c_board_info i2c3_devs[] __initdata = {
Expand Down
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