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[media] exynos4-is: Correct input DMA YUV order configuration
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This patch fixes erroneous setup of the YUV order caused by not
clearing FIMC_REG_MSCTRL_ORDER422_MASK bit field before setting
proper FIMC_REG_MSCTRL_ORDER422 bits. This resulted in false
colors for YUYV, YVYU, UYVY, VYUY color formats, depending in
what sequence those were configured by user space.
YUV order definitions are corrected so that following convention
is used:
        | byte3 | byte2 | byte1 | byte0
 -------+-------+-------+-------+------
 YCBYCR | CR    | Y     | CB    | Y
 YCRYCB | CB    | Y     | CR    | Y
 CBYCRY | Y     | CR    | Y     | CB
 CRYCBY | Y     | CB    | Y     | CR

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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Sylwester Nawrocki authored and Mauro Carvalho Chehab committed Apr 4, 2013
1 parent e90ad65 commit 4397979
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Showing 3 changed files with 18 additions and 17 deletions.
16 changes: 8 additions & 8 deletions drivers/media/platform/exynos4-is/fimc-core.c
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Original file line number Diff line number Diff line change
Expand Up @@ -412,34 +412,34 @@ void fimc_set_yuv_order(struct fimc_ctx *ctx)
/* Set order for 1 plane input formats. */
switch (ctx->s_frame.fmt->color) {
case FIMC_FMT_YCRYCB422:
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
break;
case FIMC_FMT_CBYCRY422:
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
break;
case FIMC_FMT_CRYCBY422:
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
break;
case FIMC_FMT_YCBYCR422:
default:
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
break;
}
dbg("ctx->in_order_1p= %d", ctx->in_order_1p);

switch (ctx->d_frame.fmt->color) {
case FIMC_FMT_YCRYCB422:
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
break;
case FIMC_FMT_CBYCRY422:
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
break;
case FIMC_FMT_CRYCBY422:
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
break;
case FIMC_FMT_YCBYCR422:
default:
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
break;
}
dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
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3 changes: 2 additions & 1 deletion drivers/media/platform/exynos4-is/fimc-reg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -449,7 +449,8 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
| FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK
| FIMC_REG_MSCTRL_INPUT_MASK
| FIMC_REG_MSCTRL_C_INT_IN_MASK
| FIMC_REG_MSCTRL_2P_IN_ORDER_MASK);
| FIMC_REG_MSCTRL_2P_IN_ORDER_MASK
| FIMC_REG_MSCTRL_ORDER422_MASK);

cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
| FIMC_REG_MSCTRL_INPUT_MEMORY
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16 changes: 8 additions & 8 deletions drivers/media/platform/exynos4-is/fimc-reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -95,10 +95,10 @@
/* Output DMA control */
#define FIMC_REG_CIOCTRL 0x4c
#define FIMC_REG_CIOCTRL_ORDER422_MASK (3 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_CRYCBY (0 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_CBYCRY (1 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_YCRYCB (2 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_YCBYCR (3 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_YCBYCR (0 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_YCRYCB (1 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_CBYCRY (2 << 0)
#define FIMC_REG_CIOCTRL_ORDER422_CRYCBY (3 << 0)
#define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
#define FIMC_REG_CIOCTRL_YCBCR_3PLANE (0 << 3)
#define FIMC_REG_CIOCTRL_YCBCR_2PLANE (1 << 3)
Expand Down Expand Up @@ -220,10 +220,10 @@
#define FIMC_REG_MSCTRL_FLIP_180 (3 << 13)
#define FIMC_REG_MSCTRL_FIFO_CTRL_FULL (1 << 12)
#define FIMC_REG_MSCTRL_ORDER422_SHIFT 4
#define FIMC_REG_MSCTRL_ORDER422_YCBYCR (0 << 4)
#define FIMC_REG_MSCTRL_ORDER422_CBYCRY (1 << 4)
#define FIMC_REG_MSCTRL_ORDER422_YCRYCB (2 << 4)
#define FIMC_REG_MSCTRL_ORDER422_CRYCBY (3 << 4)
#define FIMC_REG_MSCTRL_ORDER422_CRYCBY (0 << 4)
#define FIMC_REG_MSCTRL_ORDER422_YCRYCB (1 << 4)
#define FIMC_REG_MSCTRL_ORDER422_CBYCRY (2 << 4)
#define FIMC_REG_MSCTRL_ORDER422_YCBYCR (3 << 4)
#define FIMC_REG_MSCTRL_ORDER422_MASK (3 << 4)
#define FIMC_REG_MSCTRL_INPUT_EXTCAM (0 << 3)
#define FIMC_REG_MSCTRL_INPUT_MEMORY (1 << 3)
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