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[ARM] S3C64XX: Fix MMC0 clock source register mask
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Fix the definition of the MMC0 register shift and mask in the
CLKSRC register.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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Ben Dooks committed Dec 15, 2008
1 parent 6a5f4b8 commit 44539a7
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions arch/arm/plat-s3c64xx/include/plat/regs-clock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -205,8 +205,8 @@
#define S3C6400_CLKSRC_MMC2_SHIFT (22)
#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
#define S3C6400_CLKSRC_MMC1_SHIFT (20)
#define S3C6400_CLKSRC_MMC0_MASK (0xf << 1)
#define S3C6400_CLKSRC_MMC0_SHIFT (1)
#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
#define S3C6400_CLKSRC_MMC0_SHIFT (18)
#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
#define S3C6400_CLKSRC_SPI1_SHIFT (16)
#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
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