---

yaml
---
r: 212487
b: refs/heads/master
c: cb809b1
h: refs/heads/master
i:
  212485: 8a82e0f
  212483: f7b0ef0
  212479: 493f017
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a6e016f19d393fbe4e040bee8155b03b840fa689
+refs/heads/master: cb809b1a5ebffca8cf0314b788919989e8e4ab5f

trunk/arch/arm/mach-at91/include/mach/at91x40.h

@@ -52,4 +52,10 @@
 #define AT91_DBGU_CIDR	(AT91_SF + 0)	/* CIDR in PS segment */
 #define AT91_DBGU_EXID	(AT91_SF + 4)	/* EXID in PS segment */
 
+/*
+ * Support defines for the simple Power Controller module.
+ */
+#define	AT91_PS_CR	(AT91_PS + 0)	/* PS Control register */
+#define	AT91_PS_CR_CPU	(1 << 0)	/* CPU clock disable bit */
+
 #endif /* AT91X40_H */

trunk/arch/arm/mach-at91/include/mach/system.h

@@ -33,7 +33,11 @@ static inline void arch_idle(void)
 	 * Disable the processor clock.  The processor will be automatically
 	 * re-enabled by an interrupt or by a reset.
 	 */
+#ifdef AT91_PS
+	at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
+#else
 	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+#endif
 #else
 	/*
 	 * Set the processor (CP15) into 'Wait for Interrupt' mode.