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yaml
---
r: 72885
b: refs/heads/master
c: 41241c1
h: refs/heads/master
i:
  72883: 7a9ad90
v: v3
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Mike Frysinger authored and Bryan Wu committed Oct 30, 2007
1 parent 5175be1 commit 45baa2f
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2 changes: 1 addition & 1 deletion [refs]
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refs/heads/master: 36208059c18cd5e8c89fc9037cb1a79e62733882
refs/heads/master: 41241c17eb11df08efa81727f9c01225cd0f56b3
3 changes: 3 additions & 0 deletions trunk/include/asm-blackfin/mach-bf561/defBF561.h
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/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define SWRST SICA_SWRST
#define SYSCR SICA_SYSCR
#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
#define RESET_SOFTWARE (SWRST_OCCURRED)

/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */
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