Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 340038
b: refs/heads/master
c: 5ab134a
h: refs/heads/master
v: v3
  • Loading branch information
Joseph Lo authored and Stephen Warren committed Nov 5, 2012
1 parent 7967a03 commit 46ce3d4
Show file tree
Hide file tree
Showing 3 changed files with 19 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: d534b5d4a530d2d1597c3ffb9e896a3499da6172
refs/heads/master: 5ab134ad09988ca8225e759a052df7a1bbd26145
9 changes: 9 additions & 0 deletions trunk/arch/arm/boot/dts/tegra20.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,15 @@
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;

cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
arm,tag-latency = <4 4 2>;
cache-unified;
cache-level = <2>;
};

intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
Expand Down
9 changes: 9 additions & 0 deletions trunk/arch/arm/boot/dts/tegra30.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,15 @@
compatible = "nvidia,tegra30";
interrupt-parent = <&intc>;

cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <6 6 2>;
arm,tag-latency = <5 5 2>;
cache-unified;
cache-level = <2>;
};

intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
Expand Down

0 comments on commit 46ce3d4

Please sign in to comment.