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yaml
---
r: 322819
b: refs/heads/master
c: 3ec18cd
h: refs/heads/master
i:
  322817: 7054750
  322815: 377639e
v: v3
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Stephane Eranian authored and Ingo Molnar committed Sep 4, 2012
1 parent 1648d21 commit 4795f9d
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Showing 3 changed files with 4 additions and 2 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: a6fa941d94b411bbd2b6421ffbde6db3c93e65ab
refs/heads/master: 3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
1 change: 1 addition & 0 deletions trunk/arch/x86/kernel/cpu/perf_event_intel.c
Original file line number Diff line number Diff line change
Expand Up @@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
break;

case 28: /* Atom */
case 54: /* Cedariew */
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
sizeof(hw_cache_event_ids));

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3 changes: 2 additions & 1 deletion trunk/arch/x86/kernel/cpu/perf_event_intel_lbr.c
Original file line number Diff line number Diff line change
Expand Up @@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
* to have an operational LBR which can freeze
* on PMU interrupt
*/
if (boot_cpu_data.x86_mask < 10) {
if (boot_cpu_data.x86_model == 28
&& boot_cpu_data.x86_mask < 10) {
pr_cont("LBR disabled due to erratum");
return;
}
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