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CRIS: remove SMP code
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The CRIS SMP code cannot be built since there is no (and appears to
never have been) a CONFIG_SMP Kconfig option in arch/cris/.  Remove it.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Jesper Nilsson <jespern@axis.com>
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Rabin Vincent authored and Jesper Nilsson committed Mar 25, 2015
1 parent 06aca92 commit 47a8f6f
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Showing 17 changed files with 1 addition and 638 deletions.
1 change: 0 additions & 1 deletion arch/cris/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,6 @@ config CRIS
select ARCH_WANT_IPC_PARSE_VERSION
select GENERIC_IRQ_SHOW
select GENERIC_IOMAP
select GENERIC_SMP_IDLE_THREAD if ETRAX_ARCH_V32
select GENERIC_CMOS_UPDATE
select MODULES_USE_ELF_RELA
select CLONE_BACKWARDS2
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1 change: 0 additions & 1 deletion arch/cris/arch-v32/kernel/Makefile
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Expand Up @@ -9,7 +9,6 @@ obj-y := entry.o traps.o irq.o debugport.o \
process.o ptrace.o setup.o signal.o traps.o time.o \
cache.o cacheflush.o

obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o
obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
obj-$(CONFIG_MODULES) += crisksyms.o
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32 changes: 0 additions & 32 deletions arch/cris/arch-v32/kernel/head.S
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Expand Up @@ -52,11 +52,6 @@ tstart:

GIO_INIT

#ifdef CONFIG_SMP
secondary_cpu_entry: /* Entry point for secondary CPUs */
di
#endif

;; Setup and enable the MMU. Use same configuration for both the data
;; and the instruction MMU.
;;
Expand Down Expand Up @@ -164,33 +159,6 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
nop
nop

#ifdef CONFIG_SMP
;; Read CPU ID
move 0, $srs
nop
nop
nop
move $s12, $r0
cmpq 0, $r0
beq master_cpu
nop
slave_cpu:
; Time to boot-up. Get stack location provided by master CPU.
move.d smp_init_current_idle_thread, $r1
move.d [$r1], $sp
add.d 8192, $sp
move.d ebp_start, $r0 ; Defined in linker-script.
move $r0, $ebp
jsr smp_callin
nop
master_cpu:
/* Set up entry point for secondary CPUs. The boot ROM has set up
* EBP at start of internal memory. The CPU will get there
* later when we issue an IPI to them... */
move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
move.d secondary_cpu_entry, $r1
move.d $r1, [$r0]
#endif
; Check if starting from DRAM (network->RAM boot or unpacked
; compressed kernel), or directly from flash.
lapcq ., $r0
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3 changes: 0 additions & 3 deletions arch/cris/arch-v32/kernel/irq.c
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Expand Up @@ -58,9 +58,6 @@ struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
static unsigned long irq_regs[NR_CPUS] =
{
regi_irq,
#ifdef CONFIG_SMP
regi_irq2,
#endif
};

#if NR_REAL_IRQS > 32
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5 changes: 0 additions & 5 deletions arch/cris/arch-v32/kernel/setup.c
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Expand Up @@ -63,11 +63,6 @@ int show_cpuinfo(struct seq_file *m, void *v)

info = &cpinfo[ARRAY_SIZE(cpinfo) - 1];

#ifdef CONFIG_SMP
if (!cpu_online(cpu))
return 0;
#endif

revision = rdvr();

for (i = 0; i < ARRAY_SIZE(cpinfo); i++) {
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