---

yaml
---
r: 210063
b: refs/heads/master
c: c45bd37
h: refs/heads/master
i:
  210061: 15dfae3
  210059: e5d60e3
  210055: 45b1c56
  210047: 6461ab6
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a4192d32ae6788dc607e96fa85f9c9c8274e2212
+refs/heads/master: c45bd374e560873f2fff392769b9576c4f3bad40

trunk/arch/arm/mach-omap2/include/mach/entry-macro.S

@@ -177,7 +177,10 @@ omap_irq_base:	.word	0
 		cmpne   \irqnr, \tmp
 		cmpcs   \irqnr, \irqnr
 		.endm
+#endif
+#endif	/* MULTI_OMAP2 */
 
+#ifdef CONFIG_SMP
 		/* We assume that irqstat (the raw value of the IRQ acknowledge
 		 * register) is preserved from the macro above.
 		 * If there is an IPI, we immediately signal end of interrupt
@@ -205,8 +208,7 @@ omap_irq_base:	.word	0
 		streq	\irqstat, [\base, #GIC_CPU_EOI]
 		cmp	\tmp, #0
 		.endm
-#endif
-#endif	/* MULTI_OMAP2 */
+#endif	/* CONFIG_SMP */
 
 		.macro	irq_prio_table
 		.endm