---

yaml
---
r: 345079
b: refs/heads/master
c: 9473c8f
h: refs/heads/master
i:
  345077: 400e8a4
  345075: 635e95e
  345071: 73019a1
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3bcedbe5f2a3da65326d99803cac71c1e89bc93f
+refs/heads/master: 9473c8f485e1e3740d5aebf1de4838b615f9dedc

trunk/drivers/gpu/drm/i915/intel_dp.c

@@ -286,6 +286,10 @@ intel_hrawclk(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t clkcfg;
 
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
 	clkcfg = I915_READ(CLKCFG);
 	switch (clkcfg & CLKCFG_FSB_MASK) {
 	case CLKCFG_FSB_400:
@@ -366,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_GEN6(dev) || IS_GEN7(dev))
+		if (IS_VALLEYVIEW(dev))
+			aux_clock_divider = 100;
+		else if (IS_GEN6(dev) || IS_GEN7(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */