ste_dma40: remove TIM_FOR_LINK option

This does not seem to be implemented. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
git-mirror · Oct 19, 2010 · 4a6aed3 · 4a6aed3
1 parent 20a5b6d
commit 4a6aed3
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diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
@@ -147,7 +147,6 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 };
 /* Default configuration for logical memcpy */
 struct stedma40_chan_cfg dma40_memcpy_conf_log = {
-	.channel_type = STEDMA40_NO_TIM_FOR_LINK,
 	.dir = STEDMA40_MEM_TO_MEM,
 
 	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,

diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
@@ -38,11 +38,6 @@ enum stedma40_mode_opt {
 	STEDMA40_LCHAN_SRC_LOG_DST_PHY,
 };
 
-/* Interrupt */
-#define STEDMA40_INFO_TIM_POS 10
-#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)
-#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)
-
 /* End of channel_type configuration */
 
 #define STEDMA40_ESIZE_8_BIT  0x0