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yaml
---
r: 42577
b: refs/heads/master
c: b229632
h: refs/heads/master
i:
  42575: 9a7b295
v: v3
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Yoshinori Sato authored and Paul Mundt committed Dec 6, 2006
1 parent 9cb3e90 commit 4ab2ce9
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Showing 20 changed files with 416 additions and 10 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: de39840646a223ae13a346048c280b7c871bf56e
refs/heads/master: b229632abd451ab2c797010b9788e48c9314db4f
6 changes: 5 additions & 1 deletion trunk/include/asm-sh/bugs.h
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Expand Up @@ -23,9 +23,13 @@ static void __init check_bugs(void)
cpu_data->loops_per_jiffy = loops_per_jiffy;

switch (cpu_data->type) {
case CPU_SH7604:
case CPU_SH7604 ... CPU_SH7619:
*p++ = '2';
break;
case CPU_SH7206:
*p++ = '2';
*p++ = 'a';
break;
case CPU_SH7705 ... CPU_SH7300:
*p++ = '3';
break;
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22 changes: 22 additions & 0 deletions trunk/include/asm-sh/cpu-sh2/cache.h
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Expand Up @@ -12,6 +12,7 @@

#define L1_CACHE_SHIFT 4

#if defined(CONFIG_CPU_SUBTYPE_SH7604)
#define CCR 0xfffffe92 /* Address of Cache Control Register */

#define CCR_CACHE_CE 0x01 /* Cache enable */
Expand All @@ -27,5 +28,26 @@
#define CCR_CACHE_ORA CCR_CACHE_TW
#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */

#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
#define CCR1 0xffffffec
#define CCR CCR1

#define CCR_CACHE_CE 0x01 /* Cache enable */
#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
/* 0x00000000-0x7fffffff: Write-through */
/* 0x80000000-0x9fffffff: Write-back */
/* 0xc0000000-0xdfffffff: Write-through */
#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
/* 0x00000000-0x7fffffff: Write-back */
/* 0x80000000-0x9fffffff: Write-through */
/* 0xc0000000-0xdfffffff: Write-back */
#define CCR_CACHE_CF 0x08 /* Cache invalidate */

#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_DATA_ARRAY 0xf1000000

#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
#endif
#endif /* __ASM_CPU_SH2_CACHE_H */

18 changes: 18 additions & 0 deletions trunk/include/asm-sh/cpu-sh2/freq.h
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@@ -0,0 +1,18 @@
/*
* include/asm-sh/cpu-sh2/freq.h
*
* Copyright (C) 2006 Yoshinori Sato
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_FREQ_H
#define __ASM_CPU_SH2_FREQ_H

#if defined(CONFIG_CPU_SUBTYPE_SH7619)
#define FREQCR 0xf815ff80
#endif

#endif /* __ASM_CPU_SH2_FREQ_H */

84 changes: 84 additions & 0 deletions trunk/include/asm-sh/cpu-sh2/irq.h
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#ifndef __ASM_SH_CPU_SH2_IRQ_H
#define __ASM_SH_CPU_SH2_IRQ_H

/*
*
* linux/include/asm-sh/cpu-sh2/irq.h
*
* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
* Copyright (C) 2000 Kazumoto Kojima
* Copyright (C) 2003 Paul Mundt
*
*/

#include <linux/config.h>

#if defined(CONFIG_CPU_SUBTYPE_SH7044)
#define INTC_IPRA 0xffff8348UL
#define INTC_IPRB 0xffff834aUL
#define INTC_IPRC 0xffff834cUL
#define INTC_IPRD 0xffff834eUL
#define INTC_IPRE 0xffff8350UL
#define INTC_IPRF 0xffff8352UL
#define INTC_IPRG 0xffff8354UL
#define INTC_IPRH 0xffff8356UL

#define INTC_ICR 0xffff8358UL
#define INTC_ISR 0xffff835aUL
#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
#define INTC_IPRA 0xfffffee2UL
#define INTC_IPRB 0xfffffe60UL

#define INTC_VCRA 0xfffffe62UL
#define INTC_VCRB 0xfffffe64UL
#define INTC_VCRC 0xfffffe66UL
#define INTC_VCRD 0xfffffe68UL

#define INTC_VCRWDT 0xfffffee4UL
#define INTC_VCRDIV 0xffffff0cUL
#define INTC_VCRDMA0 0xffffffa0UL
#define INTC_VCRDMA1 0xffffffa8UL

#define INTC_ICR 0xfffffee0UL
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
#define INTC_IPRA 0xf8140006UL
#define INTC_IPRB 0xf8140008UL
#define INTC_IPRC 0xf8080000UL
#define INTC_IPRD 0xf8080002UL
#define INTC_IPRE 0xf8080004UL
#define INTC_IPRF 0xf8080006UL
#define INTC_IPRG 0xf8080008UL

#define INTC_ICR0 0xf8140000UL
#define INTC_IRQCR 0xf8140002UL
#define INTC_IRQSR 0xf8140004UL

#define CMI0_IRQ 86
#define CMI1_IRQ 87

#define SCIF_ERI_IRQ 88
#define SCIF_RXI_IRQ 89
#define SCIF_BRI_IRQ 90
#define SCIF_TXI_IRQ 91
#define SCIF_IPR_ADDR INTC_IPRD
#define SCIF_IPR_POS 3
#define SCIF_PRIORITY 3

#define SCIF1_ERI_IRQ 92
#define SCIF1_RXI_IRQ 93
#define SCIF1_BRI_IRQ 94
#define SCIF1_TXI_IRQ 95
#define SCIF1_IPR_ADDR INTC_IPRD
#define SCIF1_IPR_POS 2
#define SCIF1_PRIORITY 3

#define SCIF2_BRI_IRQ 96
#define SCIF2_RXI_IRQ 97
#define SCIF2_ERI_IRQ 98
#define SCIF2_TXI_IRQ 99
#define SCIF2_IPR_ADDR INTC_IPRD
#define SCIF2_IPR_POS 1
#define SCIF2_PRIORITY 3
#endif

#endif /* __ASM_SH_CPU_SH2_IRQ_H */
16 changes: 16 additions & 0 deletions trunk/include/asm-sh/cpu-sh2/mmu_context.h
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/*
* include/asm-sh/cpu-sh2/mmu_context.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
#define __ASM_CPU_SH2_MMU_CONTEXT_H

/* No MMU */

#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */

1 change: 1 addition & 0 deletions trunk/include/asm-sh/cpu-sh2a/addrspace.h
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#include <asm/cpu-sh2/addrspace.h>
39 changes: 39 additions & 0 deletions trunk/include/asm-sh/cpu-sh2a/cache.h
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@@ -0,0 +1,39 @@
/*
* include/asm-sh/cpu-sh2a/cache.h
*
* Copyright (C) 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2A_CACHE_H
#define __ASM_CPU_SH2A_CACHE_H

#define L1_CACHE_SHIFT 4

#define CCR1 0xfffc1000
#define CCR2 0xfffc1004

/* CCR1 behaves more like the traditional CCR */
#define CCR CCR1

/*
* Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
* listed here are reserved.
*/
#define CCR_CACHE_CB 0x0000 /* Hack */
#define CCR_CACHE_OCE 0x0001
#define CCR_CACHE_WT 0x0002
#define CCR_CACHE_OCI 0x0008 /* OCF */
#define CCR_CACHE_ICE 0x0100
#define CCR_CACHE_ICI 0x0800 /* ICF */

#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_ADDRESS_ARRAY 0xf0800000

#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)

#endif /* __ASM_CPU_SH2A_CACHE_H */

1 change: 1 addition & 0 deletions trunk/include/asm-sh/cpu-sh2a/cacheflush.h
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@@ -0,0 +1 @@
#include <asm/cpu-sh2/cacheflush.h>
1 change: 1 addition & 0 deletions trunk/include/asm-sh/cpu-sh2a/dma.h
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#include <asm/cpu-sh2/dma.h>
18 changes: 18 additions & 0 deletions trunk/include/asm-sh/cpu-sh2a/freq.h
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@@ -0,0 +1,18 @@
/*
* include/asm-sh/cpu-sh2a/freq.h
*
* Copyright (C) 2006 Yoshinori Sato
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2A_FREQ_H
#define __ASM_CPU_SH2A_FREQ_H

#if defined(CONFIG_CPU_SUBTYPE_SH7206)
#define FREQCR 0xfffe0010
#endif

#endif /* __ASM_CPU_SH2A_FREQ_H */

75 changes: 75 additions & 0 deletions trunk/include/asm-sh/cpu-sh2a/irq.h
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@@ -0,0 +1,75 @@
#ifndef __ASM_SH_CPU_SH2A_IRQ_H
#define __ASM_SH_CPU_SH2A_IRQ_H

#define INTC_IPR01 0xfffe0818UL
#define INTC_IPR02 0xfffe081aUL
#define INTC_IPR05 0xfffe0820UL
#define INTC_IPR06 0xfffe0c00UL
#define INTC_IPR07 0xfffe0c02UL
#define INTC_IPR08 0xfffe0c04UL
#define INTC_IPR09 0xfffe0c06UL
#define INTC_IPR10 0xfffe0c08UL
#define INTC_IPR11 0xfffe0c0aUL
#define INTC_IPR12 0xfffe0c0cUL
#define INTC_IPR13 0xfffe0c0eUL
#define INTC_IPR14 0xfffe0c10UL

#define INTC_ICR0 0xfffe0800UL
#define INTC_ICR1 0xfffe0802UL
#define INTC_ICR2 0xfffe0804UL
#define INTC_ISR 0xfffe0806UL

#define IRQ0_IRQ 64
#define IRQ1_IRQ 65
#define IRQ2_IRQ 66
#define IRQ3_IRQ 67
#define IRQ4_IRQ 68
#define IRQ5_IRQ 69
#define IRQ6_IRQ 70
#define IRQ7_IRQ 71

#define PINT0_IRQ 80
#define PINT1_IRQ 81
#define PINT2_IRQ 82
#define PINT3_IRQ 83
#define PINT4_IRQ 84
#define PINT5_IRQ 85
#define PINT6_IRQ 86
#define PINT7_IRQ 87

#define CMI0_IRQ 140
#define CMI1_IRQ 141

#define SCIF_BRI_IRQ 240
#define SCIF_ERI_IRQ 241
#define SCIF_RXI_IRQ 242
#define SCIF_TXI_IRQ 243
#define SCIF_IPR_ADDR INTC_IPR14
#define SCIF_IPR_POS 3
#define SCIF_PRIORITY 3

#define SCIF1_BRI_IRQ 244
#define SCIF1_ERI_IRQ 245
#define SCIF1_RXI_IRQ 246
#define SCIF1_TXI_IRQ 247
#define SCIF1_IPR_ADDR INTC_IPR14
#define SCIF1_IPR_POS 2
#define SCIF1_PRIORITY 3

#define SCIF2_BRI_IRQ 248
#define SCIF2_ERI_IRQ 249
#define SCIF2_RXI_IRQ 250
#define SCIF2_TXI_IRQ 251
#define SCIF2_IPR_ADDR INTC_IPR14
#define SCIF2_IPR_POS 1
#define SCIF2_PRIORITY 3

#define SCIF3_BRI_IRQ 252
#define SCIF3_ERI_IRQ 253
#define SCIF3_RXI_IRQ 254
#define SCIF3_TXI_IRQ 255
#define SCIF3_IPR_ADDR INTC_IPR14
#define SCIF3_IPR_POS 0
#define SCIF3_PRIORITY 3

#endif /* __ASM_SH_CPU_SH2A_IRQ_H */
1 change: 1 addition & 0 deletions trunk/include/asm-sh/cpu-sh2a/mmu_context.h
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@@ -0,0 +1 @@
#include <asm/cpu-sh2/mmu_context.h>
1 change: 1 addition & 0 deletions trunk/include/asm-sh/cpu-sh2a/timer.h
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@@ -0,0 +1 @@
#include <asm/cpu-sh2/timer.h>
1 change: 1 addition & 0 deletions trunk/include/asm-sh/cpu-sh2a/ubc.h
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#include <asm/cpu-sh2/ubc.h>
1 change: 1 addition & 0 deletions trunk/include/asm-sh/cpu-sh2a/watchdog.h
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#include <asm/cpu-sh2/watchdog.h>
32 changes: 32 additions & 0 deletions trunk/include/asm-sh/entry-macros.S
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@@ -0,0 +1,32 @@
! entry.S macro define
.macro cli
stc sr, r0
or #0xf0, r0
ldc r0, sr
.endm

.macro sti
mov #0xf0, r11
extu.b r11, r11
not r11, r11
stc sr, r10
and r11, r10
#ifdef CONFIG_HAS_SR_RB
stc k_g_imask, r11
or r11, r10
#endif
ldc r10, sr
.endm

.macro get_current_thread_info, ti, tmp
#ifdef CONFIG_HAS_SR_RB
stc r7_bank, \ti
#else
mov #((THREAD_SIZE - 1)>> 8) ^ 0xff, \tmp
shll8 \tmp
mov r15, \ti
and \tmp, \ti
#endif
.endm

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