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yaml --- r: 261915 b: refs/heads/master c: d0459e1 h: refs/heads/master i: 261913: 5809cb7 261911: d517551 v: v3
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Paul Mundt
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Jun 16, 2011
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--- | ||
refs/heads/master: 090b91805a97f58a7deff0f2b40aad1cc2f1b7e0 | ||
refs/heads/master: d0459e1afa58a225f074d85226bf0d7b9e54eff3 |
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#ifndef __CPU_SH3_SERIAL_H | ||
#define __CPU_SH3_SERIAL_H | ||
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#include <linux/serial_sci.h> | ||
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extern struct plat_sci_port_ops sh770x_sci_port_ops; | ||
extern struct plat_sci_port_ops sh7710_sci_port_ops; | ||
extern struct plat_sci_port_ops sh7720_sci_port_ops; | ||
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#endif /* __CPU_SH3_SERIAL_H */ |
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#ifndef __CPU_SH4A_SERIAL_H | ||
#define __CPU_SH4A_SERIAL_H | ||
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/* arch/sh/kernel/cpu/sh4a/serial-sh7722.c */ | ||
extern struct plat_sci_port_ops sh7722_sci_port_ops; | ||
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#endif /* __CPU_SH4A_SERIAL_H */ |
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#include <linux/serial_sci.h> | ||
#include <linux/serial_core.h> | ||
#include <linux/io.h> | ||
#include <cpu/serial.h> | ||
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#define SCPCR 0xA4000116 | ||
#define SCPDR 0xA4000136 | ||
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static void sh770x_sci_init_pins(struct uart_port *port, unsigned int cflag) | ||
{ | ||
unsigned short data; | ||
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/* We need to set SCPCR to enable RTS/CTS */ | ||
data = __raw_readw(SCPCR); | ||
/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ | ||
__raw_writew(data & 0x0fcf, SCPCR); | ||
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if (!(cflag & CRTSCTS)) { | ||
/* We need to set SCPCR to enable RTS/CTS */ | ||
data = __raw_readw(SCPCR); | ||
/* Clear out SCP7MD1,0, SCP4MD1,0, | ||
Set SCP6MD1,0 = {01} (output) */ | ||
__raw_writew((data & 0x0fcf) | 0x1000, SCPCR); | ||
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data = __raw_readb(SCPDR); | ||
/* Set /RTS2 (bit6) = 0 */ | ||
__raw_writeb(data & 0xbf, SCPDR); | ||
} | ||
} | ||
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struct plat_sci_port_ops sh770x_sci_port_ops = { | ||
.init_pins = sh770x_sci_init_pins, | ||
}; |
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#include <linux/serial_sci.h> | ||
#include <linux/serial_core.h> | ||
#include <linux/io.h> | ||
#include <cpu/serial.h> | ||
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#define PACR 0xa4050100 | ||
#define PBCR 0xa4050102 | ||
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static void sh7710_sci_init_pins(struct uart_port *port, unsigned int cflag) | ||
{ | ||
if (port->mapbase == 0xA4400000) { | ||
__raw_writew(__raw_readw(PACR) & 0xffc0, PACR); | ||
__raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); | ||
} else if (port->mapbase == 0xA4410000) | ||
__raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); | ||
} | ||
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struct plat_sci_port_ops sh7710_sci_port_ops = { | ||
.init_pins = sh7710_sci_init_pins, | ||
}; |
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#include <linux/serial_sci.h> | ||
#include <linux/serial_core.h> | ||
#include <linux/io.h> | ||
#include <cpu/serial.h> | ||
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static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag) | ||
{ | ||
unsigned short data; | ||
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if (cflag & CRTSCTS) { | ||
/* enable RTS/CTS */ | ||
if (port->mapbase == 0xa4430000) { /* SCIF0 */ | ||
/* Clear PTCR bit 9-2; enable all scif pins but sck */ | ||
data = __raw_readw(PORT_PTCR); | ||
__raw_writew((data & 0xfc03), PORT_PTCR); | ||
} else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | ||
/* Clear PVCR bit 9-2 */ | ||
data = __raw_readw(PORT_PVCR); | ||
__raw_writew((data & 0xfc03), PORT_PVCR); | ||
} | ||
} else { | ||
if (port->mapbase == 0xa4430000) { /* SCIF0 */ | ||
/* Clear PTCR bit 5-2; enable only tx and rx */ | ||
data = __raw_readw(PORT_PTCR); | ||
__raw_writew((data & 0xffc3), PORT_PTCR); | ||
} else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | ||
/* Clear PVCR bit 5-2 */ | ||
data = __raw_readw(PORT_PVCR); | ||
__raw_writew((data & 0xffc3), PORT_PVCR); | ||
} | ||
} | ||
} | ||
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struct plat_sci_port_ops sh7720_sci_port_ops = { | ||
.init_pins = sh7720_sci_init_pins, | ||
}; |
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