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yaml
---
r: 205423
b: refs/heads/master
c: 76cbd8a
h: refs/heads/master
i:
  205421: 5b919f8
  205419: 515e4fa
  205415: 0fa3b09
  205407: 49d684a
v: v3
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Michael Neuling authored and Ingo Molnar committed Jun 9, 2010
1 parent deffe13 commit 4b70a2e
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Showing 3 changed files with 12 additions and 2 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 532cb4c401e225b084c14d6bd6a2f8ee561de2f1
refs/heads/master: 76cbd8a8f8b0dddbff89a6708bd5bd13c0d21a00
3 changes: 2 additions & 1 deletion trunk/arch/powerpc/include/asm/cputable.h
Original file line number Diff line number Diff line change
Expand Up @@ -197,6 +197,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)

#ifndef __ASSEMBLY__

Expand Down Expand Up @@ -412,7 +413,7 @@ extern const char *powerpc_base_platform;
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
CPU_FTR_DSCR | CPU_FTR_SAO)
CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT)
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Expand Down
9 changes: 9 additions & 0 deletions trunk/arch/powerpc/kernel/process.c
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Expand Up @@ -1268,3 +1268,12 @@ unsigned long randomize_et_dyn(unsigned long base)

return ret;
}

int arch_sd_sibiling_asym_packing(void)
{
if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
return SD_ASYM_PACKING;
}
return 0;
}

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