drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIP…

…I_PORT_CTRL

LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case
of dual link. In the dual link implementation, the bit is correctly set
or unset for hardcoded PORT_A, but for bit update the register base value
is read by using MIPI_PORT_CTRL(port) in a loop. The second iteration will
read base value from PORT_C and program for PORT_A. Mostly in case of dual
link all other bit values should be same, but logically we should read from
PORT_A. So hardcode to read initial value from PORT_A as well.

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

drivers/gpu/drm/i915/intel_dsi.c

@@ -360,12 +360,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 		usleep_range(2500, 3000);
 
-		val = I915_READ(MIPI_PORT_CTRL(port));
-
 		/* Enable MIPI PHY transparent latch
 		 * Common bit for both MIPI Port A & MIPI Port C
 		 * No similar bit in MIPI Port C reg
 		 */
+		val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 		usleep_range(1000, 1500);
 
@@ -543,10 +542,10 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 							== 0x00000), 30))
 			DRM_ERROR("DSI LP not going Low\n");
 
-		val = I915_READ(MIPI_PORT_CTRL(port));
 		/* Disable MIPI PHY transparent latch
 		 * Common bit for both MIPI Port A & MIPI Port C
 		 */
+		val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
 		usleep_range(1000, 1500);