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yaml --- r: 272678 b: refs/heads/master c: 489bcce h: refs/heads/master v: v3
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Mattias Wallin
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Linus Walleij
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Sep 22, 2011
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--- | ||
refs/heads/master: cba13830d3fcb1e025e224c496a10515a39a7f80 | ||
refs/heads/master: 489bccea6334514a8e13436f10d0a274777bf17a |
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/* | ||
* Copyright (C) ST-Ericsson SA 2011 | ||
* | ||
* License Terms: GNU General Public License v2 | ||
* Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson | ||
* Author: Sundar Iyer for ST-Ericsson | ||
* sched_clock implementation is based on: | ||
* plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com> | ||
* | ||
* DBx500-PRCMU Timer | ||
* The PRCMU has 5 timers which are available in a always-on | ||
* power domain. We use the Timer 4 for our always-on clock | ||
* source on DB8500 and Timer 3 on DB5500. | ||
*/ | ||
#include <linux/clockchips.h> | ||
#include <linux/clksrc-dbx500-prcmu.h> | ||
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#include <asm/sched_clock.h> | ||
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#include <mach/setup.h> | ||
#include <mach/hardware.h> | ||
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#define RATE_32K 32768 | ||
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#define TIMER_MODE_CONTINOUS 0x1 | ||
#define TIMER_DOWNCOUNT_VAL 0xffffffff | ||
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#define PRCMU_TIMER_REF 0 | ||
#define PRCMU_TIMER_DOWNCOUNT 0x4 | ||
#define PRCMU_TIMER_MODE 0x8 | ||
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#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */ | ||
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void __iomem *clksrc_dbx500_timer_base; | ||
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static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs) | ||
{ | ||
u32 count, count2; | ||
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do { | ||
count = readl(clksrc_dbx500_timer_base + | ||
PRCMU_TIMER_DOWNCOUNT); | ||
count2 = readl(clksrc_dbx500_timer_base + | ||
PRCMU_TIMER_DOWNCOUNT); | ||
} while (count2 != count); | ||
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/* Negate because the timer is a decrementing counter */ | ||
return ~count; | ||
} | ||
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static struct clocksource clocksource_dbx500_prcmu = { | ||
.name = "dbx500-prcmu-timer", | ||
.rating = 300, | ||
.read = clksrc_dbx500_prcmu_read, | ||
.shift = 10, | ||
.mask = CLOCKSOURCE_MASK(32), | ||
.flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
}; | ||
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#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | ||
static DEFINE_CLOCK_DATA(cd); | ||
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unsigned long long notrace sched_clock(void) | ||
{ | ||
u32 cyc; | ||
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if (unlikely(!clksrc_dbx500_timer_base)) | ||
return 0; | ||
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cyc = clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu); | ||
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return cyc_to_sched_clock(&cd, cyc, (u32)~0); | ||
} | ||
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static void notrace clksrc_dbx500_prcmu_update_sched_clock(void) | ||
{ | ||
u32 cyc = clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu); | ||
update_sched_clock(&cd, cyc, (u32)~0); | ||
} | ||
#endif | ||
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void __init clksrc_dbx500_prcmu_init(void) | ||
{ | ||
/* | ||
* The A9 sub system expects the timer to be configured as | ||
* a continous looping timer. | ||
* The PRCMU should configure it but if it for some reason | ||
* don't we do it here. | ||
*/ | ||
if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) != | ||
TIMER_MODE_CONTINOUS) { | ||
writel(TIMER_MODE_CONTINOUS, | ||
clksrc_dbx500_timer_base + PRCMU_TIMER_MODE); | ||
writel(TIMER_DOWNCOUNT_VAL, | ||
clksrc_dbx500_timer_base + PRCMU_TIMER_REF); | ||
} | ||
#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | ||
init_sched_clock(&cd, clksrc_dbx500_prcmu_update_sched_clock, | ||
32, RATE_32K); | ||
#endif | ||
clocksource_calc_mult_shift(&clocksource_dbx500_prcmu, | ||
RATE_32K, SCHED_CLOCK_MIN_WRAP); | ||
clocksource_register(&clocksource_dbx500_prcmu); | ||
} |
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/* | ||
* Copyright (C) ST-Ericsson SA 2011 | ||
* | ||
* License Terms: GNU General Public License v2 | ||
* Author: Mattias Wallin <mattias.wallin@stericsson.com> | ||
* | ||
*/ | ||
#ifndef __CLKSRC_DBX500_PRCMU_H | ||
#define __CLKSRC_DBX500_PRCMU_H | ||
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#include <linux/init.h> | ||
#include <linux/io.h> | ||
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extern void __iomem *clksrc_dbx500_timer_base; | ||
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#ifdef CONFIG_CLKSRC_DBX500_PRCMU | ||
void __init clksrc_dbx500_prcmu_init(void); | ||
#else | ||
void __init clksrc_dbx500_prcmu_init(void) {} | ||
#endif | ||
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#endif |