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yaml --- r: 326655 b: refs/heads/master c: 59b0f68 h: refs/heads/master i: 326653: dc0647d 326651: 915cf6a 326647: fbd6dce 326639: 8eaeeac 326623: 3398f82 326591: 769cb0a 326527: 4f88230 326399: 0640209 326143: 789f872 325631: 5c660b6 v: v3
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refs/heads/master: c2be5bfcc986e688c0c9b427b9fb33be178437d8 | ||
refs/heads/master: 59b0f6825c15d24859e22b1024440ae2a094983e |
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/* | ||
* Copyright (c) 2012, NVIDIA Corporation. All rights reserved. | ||
* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms and conditions of the GNU General Public License, | ||
* version 2, as published by the Free Software Foundation. | ||
* | ||
* This program is distributed in the hope it will be useful, but WITHOUT | ||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
* more details. | ||
* | ||
* You should have received a copy of the GNU General Public License | ||
* along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
*/ | ||
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#include <linux/linkage.h> | ||
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#include <asm/assembler.h> | ||
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#include <mach/iomap.h> | ||
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#include "sleep.h" | ||
#include "flowctrl.h" | ||
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#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ | ||
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) | ||
/* | ||
* tegra30_hotplug_shutdown(void) | ||
* | ||
* Powergates the current CPU. | ||
* Should never return. | ||
*/ | ||
ENTRY(tegra30_hotplug_shutdown) | ||
/* Turn off SMP coherency */ | ||
exit_smp r4, r5 | ||
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/* Powergate this CPU */ | ||
mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN | ||
bl tegra30_cpu_shutdown | ||
mov pc, lr @ should never get here | ||
ENDPROC(tegra30_hotplug_shutdown) | ||
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/* | ||
* tegra30_cpu_shutdown(unsigned long flags) | ||
* | ||
* Puts the current CPU in wait-for-event mode on the flow controller | ||
* and powergates it -- flags (in R0) indicate the request type. | ||
* Must never be called for CPU 0. | ||
* | ||
* corrupts r0-r4, r12 | ||
*/ | ||
ENTRY(tegra30_cpu_shutdown) | ||
cpu_id r3 | ||
cmp r3, #0 | ||
moveq pc, lr @ Must never be called for CPU 0 | ||
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ldr r12, =TEGRA_FLOW_CTRL_VIRT | ||
cpu_to_csr_reg r1, r3 | ||
add r1, r1, r12 @ virtual CSR address for this CPU | ||
cpu_to_halt_reg r2, r3 | ||
add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU | ||
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/* | ||
* Clear this CPU's "event" and "interrupt" flags and power gate | ||
* it when halting but not before it is in the "WFE" state. | ||
*/ | ||
movw r12, \ | ||
FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ | ||
FLOW_CTRL_CSR_ENABLE | ||
mov r4, #(1 << 4) | ||
orr r12, r12, r4, lsl r3 | ||
str r12, [r1] | ||
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/* Halt this CPU. */ | ||
mov r3, #0x400 | ||
delay_1: | ||
subs r3, r3, #1 @ delay as a part of wfe war. | ||
bge delay_1; | ||
cpsid a @ disable imprecise aborts. | ||
ldr r3, [r1] @ read CSR | ||
str r3, [r1] @ clear CSR | ||
tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN | ||
movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug | ||
str r3, [r2] | ||
ldr r0, [r2] | ||
b wfe_war | ||
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__cpu_reset_again: | ||
dsb | ||
.align 5 | ||
wfe @ CPU should be power gated here | ||
wfe_war: | ||
b __cpu_reset_again | ||
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/* | ||
* 38 nop's, which fills reset of wfe cache line and | ||
* 4 more cachelines with nop | ||
*/ | ||
.rept 38 | ||
nop | ||
.endr | ||
b . @ should never get here | ||
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ENDPROC(tegra30_cpu_shutdown) | ||
#endif |
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