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…/git/mchehab/linux-2.6 * 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6: (120 commits) cx231xx: Convert to snd_card_create() V4L/DVB (11440): PWC: fix build error when CONFIG_INPUT=m V4L/DVB (11439): UVC: uvc_status_cleanup(): undefined reference to `input_unregister_device' V4L/DVB (11438): au0828: fix Kconfig dependance V4L/DVB (11437): pvrusb2: Drop client_register/unregister stubs V4L/DVB (11436): radio-mr800: convert to to v4l2_device V4L/DVB (11435): dsbr100 radio: convert to to v4l2_device V4L/DVB: zr364xx: remove unused #include <version.h> V4L/DVB: usbvision: remove unused #include <version.h> V4L/DVB (11427): gspca - m5602: Minor cleanups V4L/DVB (11426): gspca - m5602: Don't touch hflip/vflip register on Read/Modify/Write V4L/DVB (11425): gspca - m5602: Move the vflip quirk to probe stage. V4L/DVB (11424): gspca - m5602-ov9650: Use the local ctrl cache. Adjust image on vflip. V4L/DVB (11423): gspca - m5602-ov9650: Add a disconnect hook, setup a ctrl cache ctrl. V4L/DVB (11422): gspca - m5602-ov9650: Replace a magic constant with a define V4L/DVB (11421): gspca - m5602-ov9650: Synthesize modesetting. V4L/DVB (11420): gspca - m5602: Improve error handling in the ov9650 driver V4L/DVB (11419): gspca - m5602-ov9650: Don't read exposure data from COM1. V4L/DVB (11418): gspca - m5602-ov9650: Auto white balancing is on by default V4L/DVB (11417): gspca - m5602-ov9650: Autogain is on by default ...
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PXA-Camera Host Driver | ||
====================== | ||
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Constraints | ||
----------- | ||
a) Image size for YUV422P format | ||
All YUV422P images are enforced to have width x height % 16 = 0. | ||
This is due to DMA constraints, which transfers only planes of 8 byte | ||
multiples. | ||
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Global video workflow | ||
--------------------- | ||
a) QCI stopped | ||
Initialy, the QCI interface is stopped. | ||
When a buffer is queued (pxa_videobuf_ops->buf_queue), the QCI starts. | ||
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b) QCI started | ||
More buffers can be queued while the QCI is started without halting the | ||
capture. The new buffers are "appended" at the tail of the DMA chain, and | ||
smoothly captured one frame after the other. | ||
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Once a buffer is filled in the QCI interface, it is marked as "DONE" and | ||
removed from the active buffers list. It can be then requeud or dequeued by | ||
userland application. | ||
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Once the last buffer is filled in, the QCI interface stops. | ||
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DMA usage | ||
--------- | ||
a) DMA flow | ||
- first buffer queued for capture | ||
Once a first buffer is queued for capture, the QCI is started, but data | ||
transfer is not started. On "End Of Frame" interrupt, the irq handler | ||
starts the DMA chain. | ||
- capture of one videobuffer | ||
The DMA chain starts transfering data into videobuffer RAM pages. | ||
When all pages are transfered, the DMA irq is raised on "ENDINTR" status | ||
- finishing one videobuffer | ||
The DMA irq handler marks the videobuffer as "done", and removes it from | ||
the active running queue | ||
Meanwhile, the next videobuffer (if there is one), is transfered by DMA | ||
- finishing the last videobuffer | ||
On the DMA irq of the last videobuffer, the QCI is stopped. | ||
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b) DMA prepared buffer will have this structure | ||
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+------------+-----+---------------+-----------------+ | ||
| desc-sg[0] | ... | desc-sg[last] | finisher/linker | | ||
+------------+-----+---------------+-----------------+ | ||
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This structure is pointed by dma->sg_cpu. | ||
The descriptors are used as follows : | ||
- desc-sg[i]: i-th descriptor, transfering the i-th sg | ||
element to the video buffer scatter gather | ||
- finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN | ||
- linker: has ddadr= desc-sg[0] of next video buffer, dcmd=0 | ||
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For the next schema, let's assume d0=desc-sg[0] .. dN=desc-sg[N], | ||
"f" stands for finisher and "l" for linker. | ||
A typical running chain is : | ||
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Videobuffer 1 Videobuffer 2 | ||
+---------+----+---+ +----+----+----+---+ | ||
| d0 | .. | dN | l | | d0 | .. | dN | f | | ||
+---------+----+-|-+ ^----+----+----+---+ | ||
| | | ||
+----+ | ||
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After the chaining is finished, the chain looks like : | ||
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Videobuffer 1 Videobuffer 2 Videobuffer 3 | ||
+---------+----+---+ +----+----+----+---+ +----+----+----+---+ | ||
| d0 | .. | dN | l | | d0 | .. | dN | l | | d0 | .. | dN | f | | ||
+---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+ | ||
| | | | | ||
+----+ +----+ | ||
new_link | ||
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c) DMA hot chaining timeslice issue | ||
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As DMA chaining is done while DMA _is_ running, the linking may be done | ||
while the DMA jumps from one Videobuffer to another. On the schema, that | ||
would be a problem if the following sequence is encountered : | ||
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- DMA chain is Videobuffer1 + Videobuffer2 | ||
- pxa_videobuf_queue() is called to queue Videobuffer3 | ||
- DMA controller finishes Videobuffer2, and DMA stops | ||
=> | ||
Videobuffer 1 Videobuffer 2 | ||
+---------+----+---+ +----+----+----+---+ | ||
| d0 | .. | dN | l | | d0 | .. | dN | f | | ||
+---------+----+-|-+ ^----+----+----+-^-+ | ||
| | | | ||
+----+ +-- DMA DDADR loads DDADR_STOP | ||
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- pxa_dma_add_tail_buf() is called, the Videobuffer2 "finisher" is | ||
replaced by a "linker" to Videobuffer3 (creation of new_link) | ||
- pxa_videobuf_queue() finishes | ||
- the DMA irq handler is called, which terminates Videobuffer2 | ||
- Videobuffer3 capture is not scheduled on DMA chain (as it stopped !!!) | ||
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Videobuffer 1 Videobuffer 2 Videobuffer 3 | ||
+---------+----+---+ +----+----+----+---+ +----+----+----+---+ | ||
| d0 | .. | dN | l | | d0 | .. | dN | l | | d0 | .. | dN | f | | ||
+---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+ | ||
| | | | | ||
+----+ +----+ | ||
new_link | ||
DMA DDADR still is DDADR_STOP | ||
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- pxa_camera_check_link_miss() is called | ||
This checks if the DMA is finished and a buffer is still on the | ||
pcdev->capture list. If that's the case, the capture will be restarted, | ||
and Videobuffer3 is scheduled on DMA chain. | ||
- the DMA irq handler finishes | ||
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Note: if DMA stops just after pxa_camera_check_link_miss() reads DDADR() | ||
value, we have the guarantee that the DMA irq handler will be called back | ||
when the DMA will finish the buffer, and pxa_camera_check_link_miss() will | ||
be called again, to reschedule Videobuffer3. | ||
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-- | ||
Author: Robert Jarzmik <robert.jarzmik@free.fr> |
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/* | ||
* Exported ksyms of ARCH_MX1 | ||
* | ||
* Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com> | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
*/ | ||
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#include <linux/platform_device.h> | ||
#include <linux/module.h> | ||
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#include <mach/mx1_camera.h> | ||
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/* IMX camera FIQ handler */ | ||
EXPORT_SYMBOL(mx1_camera_sof_fiq_start); | ||
EXPORT_SYMBOL(mx1_camera_sof_fiq_end); |
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/* | ||
* Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
* | ||
* Based on linux/arch/arm/lib/floppydma.S | ||
* Copyright (C) 1995, 1996 Russell King | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
*/ | ||
#include <linux/linkage.h> | ||
#include <asm/assembler.h> | ||
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.text | ||
.global mx1_camera_sof_fiq_end | ||
.global mx1_camera_sof_fiq_start | ||
mx1_camera_sof_fiq_start: | ||
@ enable dma | ||
ldr r12, [r9] | ||
orr r12, r12, #0x00000001 | ||
str r12, [r9] | ||
@ unmask DMA interrupt | ||
ldr r12, [r8] | ||
bic r12, r12, r13 | ||
str r12, [r8] | ||
@ disable SOF interrupt | ||
ldr r12, [r10] | ||
bic r12, r12, #0x00010000 | ||
str r12, [r10] | ||
@ clear SOF flag | ||
mov r12, #0x00010000 | ||
str r12, [r11] | ||
@ return from FIQ | ||
subs pc, lr, #4 | ||
mx1_camera_sof_fiq_end: |
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Original file line number | Diff line number | Diff line change |
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/* | ||
* mx1_camera.h - i.MX1/i.MXL camera driver header file | ||
* | ||
* Copyright (c) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
* Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com> | ||
* | ||
* Based on PXA camera.h file: | ||
* Copyright (C) 2003, Intel Corporation | ||
* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
*/ | ||
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#ifndef __ASM_ARCH_CAMERA_H_ | ||
#define __ASM_ARCH_CAMERA_H_ | ||
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#define MX1_CAMERA_DATA_HIGH 1 | ||
#define MX1_CAMERA_PCLK_RISING 2 | ||
#define MX1_CAMERA_VSYNC_HIGH 4 | ||
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extern unsigned char mx1_camera_sof_fiq_start, mx1_camera_sof_fiq_end; | ||
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/** | ||
* struct mx1_camera_pdata - i.MX1/i.MXL camera platform data | ||
* @mclk_10khz: master clock frequency in 10kHz units | ||
* @flags: MX1 camera platform flags | ||
*/ | ||
struct mx1_camera_pdata { | ||
unsigned long mclk_10khz; | ||
unsigned long flags; | ||
}; | ||
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#endif /* __ASM_ARCH_CAMERA_H_ */ |
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