Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 19725
b: refs/heads/master
c: 8a052e0
h: refs/heads/master
i:
  19723: 5dafb13
v: v3
  • Loading branch information
Nicolas Pitre authored and Russell King committed Feb 1, 2006
1 parent 92830e4 commit 4fff17b
Show file tree
Hide file tree
Showing 2 changed files with 12 additions and 6 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 62500d1f8eadff078cca462dc4df035a29180383
refs/heads/master: 8a052e0bc25ff52f17b3dff150846ca9eb969162
16 changes: 11 additions & 5 deletions trunk/arch/arm/mm/proc-xscale.S
Original file line number Diff line number Diff line change
Expand Up @@ -241,7 +241,15 @@ ENTRY(xscale_flush_user_cache_range)
* it also trashes the mini I-cache used by JTAG debuggers.
*/
ENTRY(xscale_coherent_kern_range)
/* FALLTHROUGH */
bic r0, r0, #CACHELINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #CACHELINESIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr

/*
* coherent_user_range(start, end)
Expand All @@ -252,18 +260,16 @@ ENTRY(xscale_coherent_kern_range)
*
* - start - virtual start address
* - end - virtual end address
*
* Note: single I-cache line invalidation isn't used here since
* it also trashes the mini I-cache used by JTAG debuggers.
*/
ENTRY(xscale_coherent_user_range)
bic r0, r0, #CACHELINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
add r0, r0, #CACHELINESIZE
cmp r0, r1
blo 1b
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
mov pc, lr

Expand Down

0 comments on commit 4fff17b

Please sign in to comment.