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m68knommu: make 532x FEC platform addressing consistent
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If we make all FEC (ethernet) addressing consistent across all ColdFire
family members then we will be able to remove the duplicated plaform data
and use a single setup for all.

So modify the ColdFire 532x FEC addressing so that:

. FECs are numbered from 0 up
. base addresses are absolute (not relative to MBAR peripheral register)
. use a common name for IRQs used

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Greg Ungerer committed Mar 4, 2012
1 parent 4f8f9fb commit 5046954
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Showing 2 changed files with 21 additions and 8 deletions.
13 changes: 13 additions & 0 deletions arch/m68k/include/asm/m532xsim.h
Original file line number Diff line number Diff line change
Expand Up @@ -24,11 +24,18 @@
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */

#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)

#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)

#define MCF_WTM_WCR MCF_REG16(0xFC098000)

/*
Expand Down Expand Up @@ -90,6 +97,12 @@
#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */

/*
* FEC module.
*/
#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */

/*
* Timer module.
*/
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16 changes: 8 additions & 8 deletions arch/m68k/platform/532x/config.c
Original file line number Diff line number Diff line change
Expand Up @@ -35,23 +35,23 @@

static struct resource m532x_fec_resources[] = {
{
.start = 0xfc030000,
.end = 0xfc0307ff,
.start = MCFFEC_BASE0,
.end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = 64 + 36,
.end = 64 + 36,
.start = MCF_IRQ_FECRX0,
.end = MCF_IRQ_FECRX0,
.flags = IORESOURCE_IRQ,
},
{
.start = 64 + 40,
.end = 64 + 40,
.start = MCF_IRQ_FECTX0,
.end = MCF_IRQ_FECTX0,
.flags = IORESOURCE_IRQ,
},
{
.start = 64 + 42,
.end = 64 + 42,
.start = MCF_IRQ_FECENTC0,
.end = MCF_IRQ_FECENTC0,
.flags = IORESOURCE_IRQ,
},
};
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