---

yaml
---
r: 304233
b: refs/heads/master
c: 59bd234
h: refs/heads/master
i:
  304231: 139246e
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3c2d0ed221a22ce2c1c9fe1e2d6142374917642e
+refs/heads/master: 59bd234b72fc29887839d792b7d6c7e8d2a577a6

trunk/drivers/tty/serial/bfin_uart.c

@@ -594,7 +594,7 @@ static unsigned int bfin_serial_tx_empty(struct uart_port *port)
 static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
 {
 	struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-	u16 lcr = UART_GET_LCR(uart);
+	u32 lcr = UART_GET_LCR(uart);
 	if (break_state)
 		lcr |= SB;
 	else
@@ -1068,7 +1068,7 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
 	status = UART_GET_IER(uart) & (ERBFI | ETBEI);
 	if (status == (ERBFI | ETBEI)) {
 		/* ok, the port was enabled */
-		u16 lcr, clk;
+		u32 lcr, clk;
 
 		lcr = UART_GET_LCR(uart);
 
@@ -1079,20 +1079,8 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
 			else
 				*parity = 'o';
 		}
-		switch (lcr & 0x03) {
-		case 0:
-			*bits = 5;
-			break;
-		case 1:
-			*bits = 6;
-			break;
-		case 2:
-			*bits = 7;
-			break;
-		case 3:
-			*bits = 8;
-			break;
-		}
+		*bits = ((lcr & WLS_MASK) >> WLS_OFFSET) + 5;
+
 		/* Set DLAB in LCR to Access CLK */
 		UART_SET_DLAB(uart);