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yaml --- r: 65999 b: refs/heads/master c: 07bdda0 h: refs/heads/master i: 65997: 3edc45e 65995: 572e2ab 65991: 2f99e2e 65983: c4e7f6e v: v3
git-mirror · Aug 27, 2007 · 5453aed · 5453aed
1 parent ea30967
commit 5453aed
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Showing 2 changed files with 9 additions and 3 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3bebca2d20796dd3dc62c5d3e74148087c7ce5bd
+refs/heads/master: 07bdda02623d6d9078e45f6b6451bc3508878db1
diff --git a/trunk/include/asm-blackfin/cplb.h b/trunk/include/asm-blackfin/cplb.h
@@ -65,27 +65,33 @@
 
 #define MAX_CPLBS (16 * 2)
 
+#define ASYNC_MEMORY_CPLB_COVERAGE	((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
+				 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
+
 /*
 * Number of required data CPLB switchtable entries
 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
 * 1 for L1 Data Memory
+* possibly 1 for L2 Data Memory
 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
 * 1 for ASYNC Memory
 */
 
 
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
+#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
+				 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
 
 /*
 * Number of required instruction CPLB switchtable entries
 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
 * 1 for L1 Instruction Memory
+* possibly 1 for L2 Instruction Memory
 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
 */
 
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
+#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
 
 
 #define CPLB_ENABLE_ICACHE_P	0