---

yaml --- r: 8402 b: refs/heads/master c: e2afe67 h: refs/heads/master v: v3
git-mirror · Sep 10, 2005 · 54e7a02 · 54e7a02
1 parent f9e521e
commit 54e7a02
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Showing 3 changed files with 4 additions and 4 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ea0e0a4f53a75ed9d0812352c0410f6fc2a0b62a
+refs/heads/master: e2afe67453e5b1499459ee3596b1e7924a5208f5
diff --git a/trunk/include/asm-i386/div64.h b/trunk/include/asm-i386/div64.h
@@ -35,7 +35,7 @@
  */
 #define div_long_long_rem(a,b,c) div_ll_X_l_rem(a,b,c)
 
-extern inline long
+static inline long
 div_ll_X_l_rem(long long divs, long div, long *rem)
 {
 	long dum2;

diff --git a/trunk/include/asm-i386/processor.h b/trunk/include/asm-i386/processor.h
@@ -679,7 +679,7 @@ static inline void rep_nop(void)
    However we don't do prefetches for pre XP Athlons currently
    That should be fixed. */
 #define ARCH_HAS_PREFETCH
-extern inline void prefetch(const void *x)
+static inline void prefetch(const void *x)
 {
 	alternative_input(ASM_NOP4,
 			  "prefetchnta (%1)",
@@ -693,7 +693,7 @@ extern inline void prefetch(const void *x)
 
 /* 3dnow! prefetch to get an exclusive cache line. Useful for 
    spinlocks to avoid one state transition in the cache coherency protocol. */
-extern inline void prefetchw(const void *x)
+static inline void prefetchw(const void *x)
 {
 	alternative_input(ASM_NOP4,
 			  "prefetchw (%1)",