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ARM: tegra: paz00: fix wrong UART port on mini-pcie plug
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UARTC is connected to the mini-pcie port.

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Marc Dietrich authored and Olof Johansson committed Feb 6, 2012
1 parent 61ffca5 commit 55256f0
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Showing 2 changed files with 6 additions and 6 deletions.
4 changes: 2 additions & 2 deletions arch/arm/boot/dts/tegra-paz00.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -46,11 +46,11 @@
};

serial@70006200 {
status = "disable";
clock-frequency = <216000000>;
};

serial@70006300 {
clock-frequency = <216000000>;
status = "disable";
};

serial@70006400 {
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8 changes: 4 additions & 4 deletions arch/arm/mach-tegra/board-paz00.c
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Original file line number Diff line number Diff line change
Expand Up @@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
.uartclk = 216000000,
}, {
/* serial port on mini-pcie */
.membase = IO_ADDRESS(TEGRA_UARTD_BASE),
.mapbase = TEGRA_UARTD_BASE,
.irq = INT_UARTD,
.membase = IO_ADDRESS(TEGRA_UARTC_BASE),
.mapbase = TEGRA_UARTC_BASE,
.irq = INT_UARTC,
.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
.type = PORT_TEGRA,
.iotype = UPIO_MEM,
Expand Down Expand Up @@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
/* name parent rate enabled */
{ "uarta", "pll_p", 216000000, true },
{ "uartd", "pll_p", 216000000, true },
{ "uartc", "pll_p", 216000000, true },

{ "pll_p_out4", "pll_p", 24000000, true },
{ "usbd", "clk_m", 12000000, false },
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