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davinci: update pin-multiplexing support
Update MUX support to be more general and useful across multiple SoCs in the DaVinci family. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Kevin Hilman
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Apr 27, 2009
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Original file line number | Diff line number | Diff line change |
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/* | ||
* DaVinci pin multiplexing defines | ||
* Table of the DAVINCI register configurations for the PINMUX combinations | ||
* | ||
* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | ||
* | ||
* Based on linux/include/asm-arm/arch-omap/mux.h: | ||
* Copyright (C) 2003 - 2005 Nokia Corporation | ||
* | ||
* Written by Tony Lindgren | ||
* | ||
* 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
* the terms of the GNU General Public License version 2. This program | ||
* is licensed "as is" without any warranty of any kind, whether express | ||
* or implied. | ||
* | ||
* Copyright (C) 2008 Texas Instruments. | ||
*/ | ||
#ifndef __ASM_ARCH_MUX_H | ||
#define __ASM_ARCH_MUX_H | ||
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#define DAVINCI_MUX_AEAW0 0 | ||
#define DAVINCI_MUX_AEAW1 1 | ||
#define DAVINCI_MUX_AEAW2 2 | ||
#define DAVINCI_MUX_AEAW3 3 | ||
#define DAVINCI_MUX_AEAW4 4 | ||
#define DAVINCI_MUX_AECS4 10 | ||
#define DAVINCI_MUX_AECS5 11 | ||
#define DAVINCI_MUX_VLYNQWD0 12 | ||
#define DAVINCI_MUX_VLYNQWD1 13 | ||
#define DAVINCI_MUX_VLSCREN 14 | ||
#define DAVINCI_MUX_VLYNQEN 15 | ||
#define DAVINCI_MUX_HDIREN 16 | ||
#define DAVINCI_MUX_ATAEN 17 | ||
#define DAVINCI_MUX_RGB666 22 | ||
#define DAVINCI_MUX_RGB888 23 | ||
#define DAVINCI_MUX_LOEEN 24 | ||
#define DAVINCI_MUX_LFLDEN 25 | ||
#define DAVINCI_MUX_CWEN 26 | ||
#define DAVINCI_MUX_CFLDEN 27 | ||
#define DAVINCI_MUX_HPIEN 29 | ||
#define DAVINCI_MUX_1394EN 30 | ||
#define DAVINCI_MUX_EMACEN 31 | ||
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#define DAVINCI_MUX_LEVEL2 32 | ||
#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) | ||
#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) | ||
#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) | ||
#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) | ||
#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) | ||
#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) | ||
#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) | ||
#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) | ||
#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) | ||
#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) | ||
#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) | ||
#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) | ||
#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) | ||
#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) | ||
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extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); | ||
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#endif /* __ASM_ARCH_MUX_H */ | ||
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#ifndef __INC_MACH_MUX_H | ||
#define __INC_MACH_MUX_H | ||
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/* System module registers */ | ||
#define PINMUX0 0x00 | ||
#define PINMUX1 0x04 | ||
/* dm355 only */ | ||
#define PINMUX2 0x08 | ||
#define PINMUX3 0x0c | ||
#define PINMUX4 0x10 | ||
#define INTMUX 0x18 | ||
#define EVTMUX 0x1c | ||
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||
struct mux_config { | ||
const char *name; | ||
const char *mux_reg_name; | ||
const unsigned char mux_reg; | ||
const unsigned char mask_offset; | ||
const unsigned char mask; | ||
const unsigned char mode; | ||
bool debug; | ||
}; | ||
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enum davinci_dm644x_index { | ||
/* ATA and HDDIR functions */ | ||
DM644X_HDIREN, | ||
DM644X_ATAEN, | ||
DM644X_ATAEN_DISABLE, | ||
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/* HPI functions */ | ||
DM644X_HPIEN_DISABLE, | ||
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/* AEAW functions */ | ||
DM644X_AEAW, | ||
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/* Memory Stick */ | ||
DM644X_MSTK, | ||
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/* I2C */ | ||
DM644X_I2C, | ||
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/* ASP function */ | ||
DM644X_MCBSP, | ||
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/* UART1 */ | ||
DM644X_UART1, | ||
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/* UART2 */ | ||
DM644X_UART2, | ||
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/* PWM0 */ | ||
DM644X_PWM0, | ||
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/* PWM1 */ | ||
DM644X_PWM1, | ||
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/* PWM2 */ | ||
DM644X_PWM2, | ||
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/* VLYNQ function */ | ||
DM644X_VLYNQEN, | ||
DM644X_VLSCREN, | ||
DM644X_VLYNQWD, | ||
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/* EMAC and MDIO function */ | ||
DM644X_EMACEN, | ||
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/* GPIO3V[0:16] pins */ | ||
DM644X_GPIO3V, | ||
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/* GPIO pins */ | ||
DM644X_GPIO0, | ||
DM644X_GPIO3, | ||
DM644X_GPIO43_44, | ||
DM644X_GPIO46_47, | ||
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/* VPBE */ | ||
DM644X_RGB666, | ||
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/* LCD */ | ||
DM644X_LOEEN, | ||
DM644X_LFLDEN, | ||
}; | ||
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enum davinci_dm646x_index { | ||
/* ATA function */ | ||
DM646X_ATAEN, | ||
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/* AUDIO Clock */ | ||
DM646X_AUDCK1, | ||
DM646X_AUDCK0, | ||
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/* CRGEN Control */ | ||
DM646X_CRGMUX, | ||
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/* VPIF Control */ | ||
DM646X_STSOMUX_DISABLE, | ||
DM646X_STSIMUX_DISABLE, | ||
DM646X_PTSOMUX_DISABLE, | ||
DM646X_PTSIMUX_DISABLE, | ||
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/* TSIF Control */ | ||
DM646X_STSOMUX, | ||
DM646X_STSIMUX, | ||
DM646X_PTSOMUX_PARALLEL, | ||
DM646X_PTSIMUX_PARALLEL, | ||
DM646X_PTSOMUX_SERIAL, | ||
DM646X_PTSIMUX_SERIAL, | ||
}; | ||
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enum davinci_dm355_index { | ||
/* MMC/SD 0 */ | ||
DM355_MMCSD0, | ||
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/* MMC/SD 1 */ | ||
DM355_SD1_CLK, | ||
DM355_SD1_CMD, | ||
DM355_SD1_DATA3, | ||
DM355_SD1_DATA2, | ||
DM355_SD1_DATA1, | ||
DM355_SD1_DATA0, | ||
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/* I2C */ | ||
DM355_I2C_SDA, | ||
DM355_I2C_SCL, | ||
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/* ASP0 function */ | ||
DM355_MCBSP0_BDX, | ||
DM355_MCBSP0_X, | ||
DM355_MCBSP0_BFSX, | ||
DM355_MCBSP0_BDR, | ||
DM355_MCBSP0_R, | ||
DM355_MCBSP0_BFSR, | ||
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/* SPI0 */ | ||
DM355_SPI0_SDI, | ||
DM355_SPI0_SDENA0, | ||
DM355_SPI0_SDENA1, | ||
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/* IRQ muxing */ | ||
DM355_INT_EDMA_CC, | ||
DM355_INT_EDMA_TC0_ERR, | ||
DM355_INT_EDMA_TC1_ERR, | ||
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/* EDMA event muxing */ | ||
DM355_EVT8_ASP1_TX, | ||
DM355_EVT9_ASP1_RX, | ||
DM355_EVT26_MMC0_RX, | ||
}; | ||
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#ifdef CONFIG_DAVINCI_MUX | ||
/* setup pin muxing */ | ||
extern void davinci_mux_init(void); | ||
extern int davinci_mux_register(const struct mux_config *pins, | ||
unsigned long size); | ||
extern int davinci_cfg_reg(unsigned long reg_cfg); | ||
#else | ||
/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ | ||
static inline void davinci_mux_init(void) {} | ||
static inline int davinci_mux_register(const struct mux_config *pins, | ||
unsigned long size) { return 0; } | ||
static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } | ||
#endif | ||
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#endif /* __INC_MACH_MUX_H */ |
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