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yaml
---
r: 264306
b: refs/heads/master
c: dd0a028
h: refs/heads/master
v: v3
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Manuel Lauss authored and Ralf Baechle committed Sep 21, 2011
1 parent c0faed3 commit 55df7d3
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Showing 3 changed files with 5 additions and 8 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: b7867f1bfcb76c75d98d35f576fcd9d7759a96fe
refs/heads/master: dd0a028183369cccc0826199a7ccdc850ece289b
4 changes: 4 additions & 0 deletions trunk/arch/mips/alchemy/devboards/bcsr.c
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Expand Up @@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
{
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);

disable_irq_nosync(irq);

for ( ; bisr; bisr &= bisr - 1)
generic_handle_irq(bcsr_csc_base + __ffs(bisr));

enable_irq(irq);
}

/* NOTE: both the enable and mask bits must be cleared, otherwise the
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7 changes: 0 additions & 7 deletions trunk/arch/mips/alchemy/devboards/db1200/setup.c
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Expand Up @@ -23,13 +23,6 @@ void __init board_setup(void)
unsigned long freq0, clksrc, div, pfc;
unsigned short whoami;

/* Set Config[OD] (disable overlapping bus transaction):
* This gets rid of a _lot_ of spurious interrupts (especially
* wrt. IDE); but incurs ~10% performance hit in some
* cpu-bound applications.
*/
set_c0_config(1 << 19);

bcsr_init(DB1200_BCSR_PHYS_ADDR,
DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);

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