---

yaml
---
r: 141829
b: refs/heads/master
c: 68b42d1
h: refs/heads/master
i:
  141827: 1525609
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 01ab10393c510342ec4ce85df11ccfa3df06bbb2
+refs/heads/master: 68b42d1b548be1840aff7122fdebeb804daf0fa3

trunk/arch/sh/drivers/pci/ops-sh7785lcr.c

@@ -48,13 +48,8 @@ EXPORT_SYMBOL(board_pci_channels);
 
 static struct sh4_pci_address_map sh7785_pci_map = {
 	.window0	= {
-		.base	= SH7780_CS2_BASE_ADDR,
-		.size	= 0x04000000,
-	},
-
-	.window1	= {
-		.base	= SH7780_CS3_BASE_ADDR,
-		.size	= 0x04000000,
+		.base	= SH7780_CS0_BASE_ADDR,
+		.size	= 0x20000000,
 	},
 
 	.flags	= SH4_PCIC_NO_RESET,

trunk/arch/sh/drivers/pci/pci-sh7780.c

@@ -120,19 +120,15 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
 
 	/* Set IO and Mem windows to local address
 	 * Make PCI and local address the same for easy 1 to 1 mapping
-	 * Window0 = map->window0.size @ non-cached area base = SDRAM
-	 * Window1 = map->window1.size @ cached area base = SDRAM
 	 */
-	word = (CONFIG_MEMORY_SIZE - 0x00100000) | 0x00000001;
-	pci_write_reg(word, SH4_PCILSR0);
-	pci_write_reg(0x00000001, SH4_PCILSR1);
+	pci_write_reg(map->window0.size - 0xfffff, SH4_PCILSR0);
+	pci_write_reg(map->window1.size - 0xfffff, SH4_PCILSR1);
 	/* Set the values on window 0 PCI config registers */
-	word = CONFIG_MEMORY_START | (CONFIG_MEMORY_SIZE - 0x01000000);
-	pci_write_reg(word, SH4_PCILAR0);
-	pci_write_reg(word, SH7780_PCIMBAR0);
+	pci_write_reg(map->window0.base, SH4_PCILAR0);
+	pci_write_reg(map->window0.base, SH7780_PCIMBAR0);
 	/* Set the values on window 1 PCI config registers */
-	pci_write_reg(0x00000000, SH4_PCILAR1);
-	pci_write_reg(0x00000000, SH7780_PCIMBAR1);
+	pci_write_reg(map->window1.base, SH4_PCILAR1);
+	pci_write_reg(map->window1.base, SH7780_PCIMBAR1);
 
 	/* Map IO space into PCI IO window
 	 * The IO window is 64K-PCIBIOS_MIN_IO in size