---

yaml
---
r: 295519
b: refs/heads/master
c: ccdeed6
h: refs/heads/master
i:
  295517: 5d2f9ab
  295515: eed1080
  295511: fa3f226
  295503: b292bb5
  295487: d97d560
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a0008bf73c12212769b0d0b19cdec5c432de94ba
+refs/heads/master: ccdeed6281296977f67f57d048fdeec542428ce1

trunk/arch/arm/configs/imx_v4_v5_defconfig

@@ -68,7 +68,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y

trunk/arch/arm/mach-davinci/dma.c

@@ -1508,8 +1508,12 @@ static int __init edma_probe(struct platform_device *pdev)
 			goto fail;
 		}
 
+		/* Everything lives on transfer controller 1 until otherwise
+		 * specified. This way, long transfers on the low priority queue
+		 * started by the codec engine will not cause audio defects.
+		 */
 		for (i = 0; i < edma_cc[j]->num_channels; i++)
-			map_dmach_queue(j, i, info[j]->default_queue);
+			map_dmach_queue(j, i, EVENTQ_1);
 
 		queue_tc_mapping = info[j]->queue_tc_mapping;
 		queue_priority_mapping = info[j]->queue_priority_mapping;

trunk/arch/arm/mach-davinci/include/mach/edma.h

@@ -250,11 +250,6 @@ struct edma_soc_info {
 	unsigned	n_slot;
 	unsigned	n_tc;
 	unsigned	n_cc;
-	/*
-	 * Default queue is expected to be a low-priority queue.
-	 * This way, long transfers on the default queue started
-	 * by the codec engine will not cause audio defects.
-	 */
 	enum dma_event_q	default_queue;
 
 	/* Resource reservation for other cores */

trunk/arch/arm/mach-imx/mach-pcm038.c

@@ -233,7 +233,7 @@ static struct regulator_init_data sdhc1_data = {
 
 static struct regulator_consumer_supply cam_consumers[] = {
 	{
-		.dev_name = NULL,
+		.dev	= NULL,
 		.supply	= "imx_cam_vcc",
 	},
 };

trunk/arch/arm/mach-imx/mm-imx3.c

@@ -78,7 +78,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
 	return __arm_ioremap(phys_addr, size, mtype);
 }
 
-void __init imx3_init_l2x0(void)
+void imx3_init_l2x0(void)
 {
 	void __iomem *l2x0_base;
 	void __iomem *clkctl_base;

trunk/arch/arm/mach-lpc32xx/clock.c

@@ -82,7 +82,6 @@
  *   will also impact the individual peripheral rates.
  */
 
-#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/errno.h>
@@ -98,10 +97,9 @@
 #include "clock.h"
 #include "common.h"
 
-static DEFINE_SPINLOCK(global_clkregs_lock);
-
 static struct clk clk_armpll;
 static struct clk clk_usbpll;
+static DEFINE_MUTEX(clkm_lock);
 
 /*
  * Post divider values for PLLs based on selected register value
@@ -129,7 +127,7 @@ static struct clk osc_32KHz = {
 static int local_pll397_enable(struct clk *clk, int enable)
 {
 	u32 reg;
-	unsigned long timeout = jiffies + msecs_to_jiffies(10);
+	unsigned long timeout = 1 + msecs_to_jiffies(10);
 
 	reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
 
@@ -144,7 +142,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
 		/* Wait for PLL397 lock */
 		while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
 			LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
-			time_before(jiffies, timeout))
+			(timeout > jiffies))
 			cpu_relax();
 
 		if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
@@ -158,7 +156,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
 static int local_oscmain_enable(struct clk *clk, int enable)
 {
 	u32 reg;
-	unsigned long timeout = jiffies + msecs_to_jiffies(10);
+	unsigned long timeout = 1 + msecs_to_jiffies(10);
 
 	reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 
@@ -173,7 +171,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
 		/* Wait for main oscillator to start */
 		while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
 			LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
-			time_before(jiffies, timeout))
+			(timeout > jiffies))
 			cpu_relax();
 
 		if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
@@ -385,7 +383,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
 {
 	u32 reg;
 	int ret = -ENODEV;
-	unsigned long timeout = jiffies + msecs_to_jiffies(10);
+	unsigned long timeout = 1 + msecs_to_jiffies(10);
 
 	reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 
@@ -398,7 +396,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
 		__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 
 		/* Wait for PLL lock */
-		while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
+		while ((timeout > jiffies) & (ret == -ENODEV)) {
 			reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 			if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
 				ret = 0;
@@ -893,8 +891,20 @@ static struct clk clk_lcd = {
 	.enable_mask	= LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 };
 
+static inline void clk_lock(void)
+{
+	mutex_lock(&clkm_lock);
+}
+
+static inline void clk_unlock(void)
+{
+	mutex_unlock(&clkm_lock);
+}
+
 static void local_clk_disable(struct clk *clk)
 {
+	WARN_ON(clk->usecount == 0);
+
 	/* Don't attempt to disable clock if it has no users */
 	if (clk->usecount > 0) {
 		clk->usecount--;
@@ -937,11 +947,10 @@ static int local_clk_enable(struct clk *clk)
 int clk_enable(struct clk *clk)
 {
 	int ret;
-	unsigned long flags;
 
-	spin_lock_irqsave(&global_clkregs_lock, flags);
+	clk_lock();
 	ret = local_clk_enable(clk);
-	spin_unlock_irqrestore(&global_clkregs_lock, flags);
+	clk_unlock();
 
 	return ret;
 }
@@ -952,11 +961,9 @@ EXPORT_SYMBOL(clk_enable);
  */
 void clk_disable(struct clk *clk)
 {
-	unsigned long flags;
-
-	spin_lock_irqsave(&global_clkregs_lock, flags);
+	clk_lock();
 	local_clk_disable(clk);
-	spin_unlock_irqrestore(&global_clkregs_lock, flags);
+	clk_unlock();
 }
 EXPORT_SYMBOL(clk_disable);
 
@@ -965,7 +972,13 @@ EXPORT_SYMBOL(clk_disable);
  */
 unsigned long clk_get_rate(struct clk *clk)
 {
-	return clk->get_rate(clk);
+	unsigned long rate;
+
+	clk_lock();
+	rate = clk->get_rate(clk);
+	clk_unlock();
+
+	return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 
@@ -981,8 +994,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 	 * the actual rate set as part of the peripheral dividers
 	 * instead of high level clock control
 	 */
-	if (clk->set_rate)
+	if (clk->set_rate) {
+		clk_lock();
 		ret = clk->set_rate(clk, rate);
+		clk_unlock();
+	}
 
 	return ret;
 }
@@ -993,11 +1009,15 @@ EXPORT_SYMBOL(clk_set_rate);
  */
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
+	clk_lock();
+
 	if (clk->round_rate)
 		rate = clk->round_rate(clk, rate);
 	else
 		rate = clk->get_rate(clk);
 
+	clk_unlock();
+
 	return rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
@@ -1055,10 +1075,10 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
 	_REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
 	_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
-	_REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
-	_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
+	_REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
+	_REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
 	_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
-	_REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
+	_REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
 	_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
 	_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
 	_REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)

trunk/arch/arm/mach-lpc32xx/common.h

@@ -65,6 +65,7 @@ extern u32 clk_get_pclk_div(void);
  */
 extern void lpc32xx_get_uid(u32 devid[4]);
 
+extern void lpc32xx_watchdog_reset(void);
 extern u32 lpc32xx_return_iram_size(void);
 
 /*