Skip to content

Commit

Permalink
drm/exynos: fixed blending for hdmi graphic layer
Browse files Browse the repository at this point in the history
Blending for graphic layer 0 of hdmi mixer was not set so video
layer cannot be showed if graphic layer 0 is enabled.
This patch fixes blending values to support blending between
graphic layer 0 and video layer.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
  • Loading branch information
Seung-Woo Kim authored and Inki Dae committed Jun 5, 2012
1 parent f56fdce commit 5736603
Showing 1 changed file with 6 additions and 4 deletions.
10 changes: 6 additions & 4 deletions drivers/gpu/drm/exynos/exynos_mixer.c
Original file line number Diff line number Diff line change
Expand Up @@ -601,18 +601,20 @@ static void mixer_win_reset(struct mixer_context *ctx)
mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);

/* setting graphical layers */

val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
val |= MXR_GRP_CFG_WIN_BLEND_EN;
val |= MXR_GRP_CFG_BLEND_PRE_MUL;
val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */

/* the same configuration for both layers */
mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);

val |= MXR_GRP_CFG_BLEND_PRE_MUL;
val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);

/* setting video layers */
val = MXR_GRP_CFG_ALPHA_VAL(0);
mixer_reg_write(res, MXR_VIDEO_CFG, val);

/* configuration of Video Processor Registers */
vp_win_reset(ctx);
vp_default_filter(res);
Expand Down

0 comments on commit 5736603

Please sign in to comment.