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drm/nvc1/gr: update initial register/context values
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs committed Jul 1, 2013
1 parent 8b637ae commit 58ef230
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Showing 6 changed files with 80 additions and 35 deletions.
24 changes: 23 additions & 1 deletion drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1327,6 +1327,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc1:
case 0xd9:
case 0xd7:
break;
Expand Down Expand Up @@ -1475,6 +1476,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
break;
}
Expand All @@ -1496,6 +1498,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc1:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x4040d0, 0x00000000);
Expand Down Expand Up @@ -1524,6 +1527,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x404174, 0x00000000);
break;
Expand Down Expand Up @@ -1709,6 +1713,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
break;
}
Expand Down Expand Up @@ -1771,7 +1776,6 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x408900, 0x3080b801);
nv_wr32(priv, 0x408904, 0x62000001);
nv_wr32(priv, 0x408908, 0x00c80929);
nv_wr32(priv, 0x40890c, 0x00000000);
break;
case 0xd9:
case 0xd7:
Expand Down Expand Up @@ -1806,6 +1810,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x418408, 0x00000000);
break;
Expand All @@ -1819,6 +1824,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x418414, 0x00200fff);
break;
Expand All @@ -1844,6 +1850,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x41870c, 0x07c80000);
break;
Expand All @@ -1856,6 +1863,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x418800, 0x0006860a);
break;
Expand Down Expand Up @@ -1917,6 +1925,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x418b00, 0x00000000);
break;
Expand Down Expand Up @@ -1986,6 +1995,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc0:
break;
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x419a1c, 0x00000000);
nv_wr32(priv, 0x419a20, 0x00000800);
Expand All @@ -2000,6 +2010,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x00419ac4, 0x0017f440);
break;
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x00419ac4, 0x0007f440);
break;
Expand Down Expand Up @@ -2031,6 +2042,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x419c00, 0x00000002);
break;
Expand All @@ -2040,6 +2052,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419c20, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xc3:
case 0xc1:
case 0xce:
case 0xcf:
nv_wr32(priv, 0x419cb0, 0x00020048);
Expand Down Expand Up @@ -2115,6 +2128,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419ee0, 0x00010110);
break;
case 0xc3:
case 0xc1:
default:
nv_wr32(priv, 0x419ee0, 0x00011110);
break;
Expand All @@ -2126,6 +2140,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419f54, 0x00000000);
break;
case 0xc3:
case 0xc1:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419f30, 0x00000000);
Expand Down Expand Up @@ -2463,6 +2478,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
break;
}
Expand All @@ -2482,6 +2498,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc3:
case 0xc1:
break;
default:
break;
Expand Down Expand Up @@ -3049,11 +3066,13 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
nv_icmd(priv, 0x00000585, 0x0000003f);
nv_icmd(priv, 0x00000576, 0x00000003);
switch (nv_device(priv)->chipset) {
case 0xc1:
case 0xd9:
case 0xd7:
nv_icmd(priv, 0x0000057b, 0x00000059);
break;
case 0xc0:
case 0xc3:
default:
break;
}
Expand Down Expand Up @@ -3163,6 +3182,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
nv_icmd(priv, 0x0000097d, 0x00000020);
break;
case 0xc0:
case 0xc3:
case 0xc1:
default:
break;
}
Expand Down Expand Up @@ -3311,6 +3332,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xc0:
case 0xc3:
case 0xc1:
nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
break;
case 0xd9:
Expand Down
16 changes: 8 additions & 8 deletions drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,10 +53,10 @@ chipsets:
.b16 #nnvc0_tpc_mmio_head
.b16 #nnvc0_tpc_mmio_tail
.b8 0xc1 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc1_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc1_tpc_mmio_tail
.b16 #nnvc0_gpc_mmio_head
.b16 #nnvc1_gpc_mmio_tail
.b16 #nnvc3_tpc_mmio_head
.b16 #nnvc1_tpc_mmio_tail
.b8 0xc3 0 0 0
.b16 #nnvc0_gpc_mmio_head
.b16 #nnvc0_gpc_mmio_tail
Expand Down Expand Up @@ -121,8 +121,6 @@ mmctx_data(0x000c8c, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nvc0_gpc_mmio_tail:
mmctx_data(0x000c6c, 1);
nvc1_gpc_mmio_tail:

nnvc0_gpc_mmio_head:
mmctx_data(0x000380, 1)
Expand Down Expand Up @@ -150,6 +148,8 @@ mmctx_data(0x000c8c, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nnvc0_gpc_mmio_tail:
mmctx_data(0x000c6c, 1);
nnvc1_gpc_mmio_tail:

nvd9_gpc_mmio_head:
mmctx_data(0x000380, 1)
Expand Down Expand Up @@ -209,8 +209,6 @@ mmctx_data(0x0006e0, 1)
nvcf_tpc_mmio_tail:
mmctx_data(0x0004bc, 1)
nvc3_tpc_mmio_tail:
mmctx_data(0x000544, 1)
nvc1_tpc_mmio_tail:

nnvc0_tpc_mmio_head:
mmctx_data(0x000018, 1)
Expand Down Expand Up @@ -258,6 +256,8 @@ mmctx_data(0x000698, 1)
mmctx_data(0x0006e0, 1)
mmctx_data(0x000730, 11)
nnvc3_tpc_mmio_tail:
mmctx_data(0x000544, 1)
nnvc1_tpc_mmio_tail:

nvd9_tpc_mmio_head:
mmctx_data(0x000018, 1)
Expand Down
32 changes: 16 additions & 16 deletions drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,14 +34,14 @@ uint32_t nvc0_grgpc_data[] = {
0x00000000,
/* 0x0064: chipsets */
0x000000c0,
0x01980138,
0x02b00264,
0x01940134,
0x02ac0260,
0x000000c1,
0x013800d4,
0x02640200,
0x01980134,
0x030802ac,
0x000000c3,
0x01980138,
0x030802b0,
0x01940134,
0x030402ac,
0x000000c4,
0x013400d4,
0x02600200,
Expand Down Expand Up @@ -87,9 +87,7 @@ uint32_t nvc0_grgpc_data[] = {
0x08001000,
0x00001014,
/* 0x0134: nvc0_gpc_mmio_tail */
0x00000c6c,
/* 0x0138: nvc1_gpc_mmio_tail */
/* 0x0138: nnvc0_gpc_mmio_head */
/* 0x0134: nnvc0_gpc_mmio_head */
0x00000380,
0x14000400,
0x20000450,
Expand All @@ -114,7 +112,9 @@ uint32_t nvc0_grgpc_data[] = {
0x00000c8c,
0x08001000,
0x00001014,
/* 0x0198: nnvc0_gpc_mmio_tail */
/* 0x0194: nnvc0_gpc_mmio_tail */
0x00000c6c,
/* 0x0198: nnvc1_gpc_mmio_tail */
/* 0x0198: nvd9_gpc_mmio_head */
0x00000380,
0x04000400,
Expand Down Expand Up @@ -171,9 +171,7 @@ uint32_t nvc0_grgpc_data[] = {
/* 0x025c: nvcf_tpc_mmio_tail */
0x000004bc,
/* 0x0260: nvc3_tpc_mmio_tail */
0x00000544,
/* 0x0264: nvc1_tpc_mmio_tail */
/* 0x0264: nnvc0_tpc_mmio_head */
/* 0x0260: nnvc0_tpc_mmio_head */
0x00000018,
0x0000003c,
0x00000048,
Expand All @@ -193,8 +191,8 @@ uint32_t nvc0_grgpc_data[] = {
0x4c000644,
0x00000698,
0x04000750,
/* 0x02b0: nnvc0_tpc_mmio_tail */
/* 0x02b0: nnvc3_tpc_mmio_head */
/* 0x02ac: nnvc0_tpc_mmio_tail */
/* 0x02ac: nnvc3_tpc_mmio_head */
0x00000018,
0x0000003c,
0x00000048,
Expand All @@ -217,7 +215,9 @@ uint32_t nvc0_grgpc_data[] = {
0x00000698,
0x000006e0,
0x28000730,
/* 0x0308: nnvc3_tpc_mmio_tail */
/* 0x0304: nnvc3_tpc_mmio_tail */
0x00000544,
/* 0x0308: nnvc1_tpc_mmio_tail */
/* 0x0308: nvd9_tpc_mmio_head */
0x00000018,
0x0000003c,
Expand Down
6 changes: 3 additions & 3 deletions drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ chipsets:
.b16 #nnvc0_hub_mmio_head
.b16 #nnvc0_hub_mmio_tail
.b8 0xc1 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nnvc0_hub_mmio_head
.b16 #nvc1_hub_mmio_tail
.b8 0xc3 0 0 0
.b16 #nnvc0_hub_mmio_head
Expand Down Expand Up @@ -117,8 +117,6 @@ mmctx_data(0x408800, 3)
mmctx_data(0x408900, 4)
mmctx_data(0x408980, 1)
nvc0_hub_mmio_tail:
mmctx_data(0x4064c0, 2)
nvc1_hub_mmio_tail:

nnvc0_hub_mmio_head:
mmctx_data(0x17e91c, 2)
Expand Down Expand Up @@ -161,6 +159,8 @@ mmctx_data(0x408800, 3)
mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1)
nnvc0_hub_mmio_tail:
mmctx_data(0x4064c0, 2)
nvc1_hub_mmio_tail:

nvd9_hub_mmio_head:
mmctx_data(0x17e91c, 2)
Expand Down
14 changes: 7 additions & 7 deletions drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -203,11 +203,11 @@ uint32_t nvc0_grhub_data[] = {
0x00000000,
/* 0x0300: chipsets */
0x000000c0,
0x048803ec,
0x048403e8,
0x000000c1,
0x03ec034c,
0x048803e8,
0x000000c3,
0x048803ec,
0x048403e8,
0x000000c4,
0x03e8034c,
0x000000c8,
Expand Down Expand Up @@ -262,9 +262,7 @@ uint32_t nvc0_grhub_data[] = {
0x0c408900,
0x00408980,
/* 0x03e8: nvc0_hub_mmio_tail */
0x044064c0,
/* 0x03ec: nvc1_hub_mmio_tail */
/* 0x03ec: nnvc0_hub_mmio_head */
/* 0x03e8: nnvc0_hub_mmio_head */
0x0417e91c,
0x04400204,
0x28404004,
Expand Down Expand Up @@ -304,7 +302,9 @@ uint32_t nvc0_grhub_data[] = {
0x08408800,
0x08408900,
0x00408980,
/* 0x0488: nnvc0_hub_mmio_tail */
/* 0x0484: nnvc0_hub_mmio_tail */
0x044064c0,
/* 0x0488: nvc1_hub_mmio_tail */
/* 0x0488: nvd9_hub_mmio_head */
0x0417e91c,
0x04400204,
Expand Down
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