Skip to content

Commit

Permalink
drm/i915: Rename the forcewake get/put functions
Browse files Browse the repository at this point in the history 
We have multiple forcewake domains now on recent gens. Change the
function naming to reflect this.

v2: More verbose names (Chris)
v3: Rebase
v4: Rebase
v5: Add documentation for forcewake_get/put

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
  • Loading branch information
Mika Kuoppala authored and Daniel Vetter committed Jan 27, 2015
1 parent 756c349 commit 59bad94
Show file tree
Hide file tree
Showing 9 changed files with 58 additions and 52 deletions.
8 changes: 4 additions & 4 deletions drivers/gpu/drm/i915/i915_debugfs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1105,7 +1105,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
if (ret)
goto out;

gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

reqf = I915_READ(GEN6_RPNSWREQ);
reqf &= ~GEN6_TURBO_DISABLE;
Expand All @@ -1132,7 +1132,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
cagf *= GT_FREQUENCY_MULTIPLIER;

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&dev->struct_mutex);

if (IS_GEN6(dev) || IS_GEN7(dev)) {
Expand Down Expand Up @@ -4322,7 +4322,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
return 0;

intel_runtime_pm_get(dev_priv);
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

return 0;
}
Expand All @@ -4335,7 +4335,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
if (INTEL_INFO(dev)->gen < 6)
return 0;

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
intel_runtime_pm_put(dev_priv);

return 0;
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/i915/i915_drv.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1431,7 +1431,7 @@ static int intel_runtime_suspend(struct device *device)
intel_opregion_notify_adapter(dev, PCI_D3hot);
}

assert_force_wake_inactive(dev_priv);
assert_forcewakes_inactive(dev_priv);

DRM_DEBUG_KMS("Device suspended\n");
return 0;
Expand Down
15 changes: 5 additions & 10 deletions drivers/gpu/drm/i915/i915_drv.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2564,6 +2564,11 @@ extern void intel_uncore_check_errors(struct drm_device *dev);
extern void intel_uncore_fini(struct drm_device *dev);
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
const char *intel_uncore_forcewake_domain_to_str(const int domain_id);
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
unsigned fw_domains);
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
unsigned fw_domains);
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);

void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Expand Down Expand Up @@ -3195,16 +3200,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
struct drm_device *dev,
struct intel_display_error_state *error);

/* On SNB platform, before reading ring registers forcewake bit
* must be set to prevent GT core from power down and stale values being
* returned.
*/
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
unsigned fw_domains);
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
unsigned fw_domains);
void assert_force_wake_inactive(struct drm_i915_private *dev_priv);

int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);

Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/i915/intel_display.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7871,7 +7871,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
* Make sure we're not on PC8 state before disabling PC8, otherwise
* we'll hang the machine. To prevent PC8 state, just enable force_wake.
*/
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

if (val & LCPLL_POWER_DOWN_ALLOW) {
val &= ~LCPLL_POWER_DOWN_ALLOW;
Expand Down Expand Up @@ -7901,7 +7901,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
DRM_ERROR("Switching back to LCPLL failed\n");
}

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

/*
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/i915/intel_fbc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,7 @@ static void snb_fbc_blit_update(struct drm_device *dev)

/* Blitter is part of Media powerwell on VLV. No impact of
* his param in other platforms for now */
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);

blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
Expand All @@ -195,7 +195,7 @@ static void snb_fbc_blit_update(struct drm_device *dev)
I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
POSTING_READ(GEN6_BLITTER_ECOSKPD);

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
}

static void ilk_fbc_enable(struct drm_crtc *crtc)
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/i915/intel_lrc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -296,7 +296,7 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,
desc[3] = (u32)(temp >> 32);
desc[2] = (u32)temp;

gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
I915_WRITE(RING_ELSP(ring), desc[1]);
I915_WRITE(RING_ELSP(ring), desc[0]);
I915_WRITE(RING_ELSP(ring), desc[3]);
Expand All @@ -306,7 +306,7 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,

/* ELSP is a wo register, so use another nearby reg for posting instead */
POSTING_READ(RING_EXECLIST_STATUS(ring));
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
Expand Down
25 changes: 12 additions & 13 deletions drivers/gpu/drm/i915/intel_pm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,6 @@ static void gen9_init_clock_gating(struct drm_device *dev)
_MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
}


static void i915_pineview_get_mem_freq(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
Expand Down Expand Up @@ -3915,11 +3914,11 @@ static void valleyview_disable_rps(struct drm_device *dev)

/* we're doing forcewake before Disabling RC6,
* This what the BIOS expects when going into suspend */
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

I915_WRITE(GEN6_RC_CONTROL, 0);

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
Expand Down Expand Up @@ -4037,7 +4036,7 @@ static void gen9_enable_rps(struct drm_device *dev)

/* 1b: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

/* 2a: Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
Expand All @@ -4060,7 +4059,7 @@ static void gen9_enable_rps(struct drm_device *dev)
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}

Expand All @@ -4076,7 +4075,7 @@ static void gen8_enable_rps(struct drm_device *dev)

/* 1c & 1d: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

/* 2a: Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
Expand Down Expand Up @@ -4143,7 +4142,7 @@ static void gen8_enable_rps(struct drm_device *dev)
dev_priv->rps.power = HIGH_POWER; /* force a reset */
gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

static void gen6_enable_rps(struct drm_device *dev)
Expand Down Expand Up @@ -4171,7 +4170,7 @@ static void gen6_enable_rps(struct drm_device *dev)
I915_WRITE(GTFIFODBG, gtfifodbg);
}

gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

/* Initialize rps frequencies */
gen6_init_rps_frequencies(dev);
Expand Down Expand Up @@ -4251,7 +4250,7 @@ static void gen6_enable_rps(struct drm_device *dev)
DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
}

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

static void __gen6_update_ring_freq(struct drm_device *dev)
Expand Down Expand Up @@ -4710,7 +4709,7 @@ static void cherryview_enable_rps(struct drm_device *dev)

/* 1a & 1b: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

/* Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
Expand Down Expand Up @@ -4783,7 +4782,7 @@ static void cherryview_enable_rps(struct drm_device *dev)

valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

static void valleyview_enable_rps(struct drm_device *dev)
Expand All @@ -4804,7 +4803,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
}

/* If VLV, Forcewake all wells, else re-direct to regular path */
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

/* Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
Expand Down Expand Up @@ -4867,7 +4866,7 @@ static void valleyview_enable_rps(struct drm_device *dev)

valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);

gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}

void ironlake_teardown_rc6(struct drm_device *dev)
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/i915/intel_ringbuffer.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -539,7 +539,7 @@ static int init_ring_common(struct intel_engine_cs *ring)
struct drm_i915_gem_object *obj = ringbuf->obj;
int ret = 0;

gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

if (!stop_ring(ring)) {
/* G45 ring initialization often fails to reset head to zero */
Expand Down Expand Up @@ -611,7 +611,7 @@ static int init_ring_common(struct intel_engine_cs *ring)
memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));

out:
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

return ret;
}
Expand Down
44 changes: 28 additions & 16 deletions drivers/gpu/drm/i915/intel_uncore.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -234,7 +234,7 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
return ret;
}

static void gen6_force_wake_timer(unsigned long arg)
static void intel_uncore_fw_release_timer(unsigned long arg)
{
struct intel_uncore_forcewake_domain *domain = (void *)arg;
unsigned long irqflags;
Expand Down Expand Up @@ -270,7 +270,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
if (del_timer_sync(&domain->timer) == 0)
continue;

gen6_force_wake_timer((unsigned long)domain);
intel_uncore_fw_release_timer((unsigned long)domain);
}

spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Expand Down Expand Up @@ -314,7 +314,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
}

if (!restore)
assert_force_wake_inactive(dev_priv);
assert_forcewakes_inactive(dev_priv);

spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
Expand Down Expand Up @@ -358,14 +358,21 @@ void intel_uncore_sanitize(struct drm_device *dev)
intel_disable_gt_powersave(dev);
}

/*
* Generally this is called implicitly by the register read function. However,
* if some sequence requires the GT to not power down then this function should
* be called at the beginning of the sequence followed by a call to
* gen6_gt_force_wake_put() at the end of the sequence.
/**
* intel_uncore_forcewake_get - grab forcewake domain references
* @dev_priv: i915 device instance
* @fw_domains: forcewake domains to get reference on
*
* This function can be used get GT's forcewake domain references.
* Normal register access will handle the forcewake domains automatically.
* However if some sequence requires the GT to not power down a particular
* forcewake domains this function should be called at the beginning of the
* sequence. And subsequently the reference should be dropped by symmetric
* call to intel_unforce_forcewake_put(). Usually caller wants all the domains
* to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
*/
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
unsigned fw_domains)
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
unsigned fw_domains)
{
unsigned long irqflags;
struct intel_uncore_forcewake_domain *domain;
Expand All @@ -391,11 +398,16 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}

/*
* see gen6_gt_force_wake_get()
/**
* intel_uncore_forcewake_put - release a forcewake domain reference
* @dev_priv: i915 device instance
* @fw_domains: forcewake domains to put references
*
* This function drops the device-level forcewakes for specified
* domains obtained by intel_uncore_forcewake_get().
*/
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
unsigned fw_domains)
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
unsigned fw_domains)
{
unsigned long irqflags;
struct intel_uncore_forcewake_domain *domain;
Expand All @@ -422,7 +434,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}

void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
{
struct intel_uncore_forcewake_domain *domain;
int id;
Expand Down Expand Up @@ -964,7 +976,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
d->i915 = dev_priv;
d->id = domain_id;

setup_timer(&d->timer, gen6_force_wake_timer, (unsigned long)d);
setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);

dev_priv->uncore.fw_domains |= (1 << domain_id);
}
Expand Down

0 comments on commit 59bad94

Please sign in to comment.