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staging: ti dspbridge: Rename words with camel case
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The intention of this patch is to rename the remaining variables with camel
case. Variables will be renamed avoiding camel case and Hungarian notation.
The words to be renamed in this patch are:
========================================
validBit to valid_bit
victimEntryNum to victim_entry_num
virtualAddr to virtual_addr
xType to xtype
actualValue to actual_value
EASIL1_MMUMMU_IRQSTATUSReadRegister32 to easil1_mmummu_irqstatus_read_register32
EASIL1_MMUMMU_LOCKBaseValueWrite32 to easil1_mmummu_lock_base_value_write32
easiNum to easi_num
expectedValue to expected_value
invalidValue to invalid_value
L1_base to l1_base
L2_base to l2_base
lower16Bits to lower16_bits
lower8Bits to lower8_bits
lowerMiddle8Bits to lower_middle8_bits
lowerUpper8Bits to lower_upper8_bits
maxValidValue to max_valid_value
minValidValue to min_valid_value
newValue to new_value
returnCodeIfMismatch to return_code_if_mismatch
spyCodeIfMisMatch to spy_code_if_mis_match
upper16Bits to upper16_bits
upper8Bits to upper8_bits
========================================

Signed-off-by: Rene Sapiens <rene.sapiens@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Rene Sapiens authored and Greg Kroah-Hartman committed Jul 22, 2010
1 parent 5e2eae5 commit 5a09dde
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Showing 7 changed files with 129 additions and 127 deletions.
2 changes: 1 addition & 1 deletion drivers/staging/tidspbridge/hw/EasiGlobal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,6 @@
*
* NOTE: We currently dont use this functionality.
*/
#define _DEBUG_LEVEL1_EASI(easiNum) ((void)0)
#define _DEBUG_LEVEL1_EASI(easi_num) ((void)0)

#endif /* _EASIGLOBAL_H */
72 changes: 37 additions & 35 deletions drivers/staging/tidspbridge/hw/GlobalTypes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -94,39 +94,39 @@
#define LOWER8BIT_MASK 0x000000FF

/*
* Definition: RETURN32BITS_FROM16LOWER_AND16UPPER(lower16Bits, upper16Bits)
* Definition: RETURN32BITS_FROM16LOWER_AND16UPPER(lower16_bits, upper16_bits)
*
* DESCRIPTION: Returns a 32 bit value given a 16 bit lower value and a 16
* bit upper value
*/
#define RETURN32BITS_FROM16LOWER_AND16UPPER(lower16Bits, upper16Bits)\
(((((u32)lower16Bits) & LOWER16BIT_MASK)) | \
(((((u32)upper16Bits) & LOWER16BIT_MASK) << UPPER16BIT_SHIFT)))
#define RETURN32BITS_FROM16LOWER_AND16UPPER(lower16_bits, upper16_bits)\
(((((u32)lower16_bits) & LOWER16BIT_MASK)) | \
(((((u32)upper16_bits) & LOWER16BIT_MASK) << UPPER16BIT_SHIFT)))

/*
* Definition: RETURN16BITS_FROM8LOWER_AND8UPPER(lower16Bits, upper16Bits)
* Definition: RETURN16BITS_FROM8LOWER_AND8UPPER(lower16_bits, upper16_bits)
*
* DESCRIPTION: Returns a 16 bit value given a 8 bit lower value and a 8
* bit upper value
*/
#define RETURN16BITS_FROM8LOWER_AND8UPPER(lower8Bits, upper8Bits)\
(((((u32)lower8Bits) & LOWER8BIT_MASK)) | \
(((((u32)upper8Bits) & LOWER8BIT_MASK) << UPPER8BIT_OF16_SHIFT)))
#define RETURN16BITS_FROM8LOWER_AND8UPPER(lower8_bits, upper8_bits)\
(((((u32)lower8_bits) & LOWER8BIT_MASK)) | \
(((((u32)upper8_bits) & LOWER8BIT_MASK) << UPPER8BIT_OF16_SHIFT)))

/*
* Definition: RETURN32BITS_FROM48BIT_VALUES(lower8Bits, lowerMiddle8Bits,
* lowerUpper8Bits, upper8Bits)
* Definition: RETURN32BITS_FROM48BIT_VALUES(lower8_bits, lower_middle8_bits,
* lower_upper8_bits, upper8_bits)
*
* DESCRIPTION: Returns a 32 bit value given four 8 bit values
*/
#define RETURN32BITS_FROM48BIT_VALUES(lower8Bits, lowerMiddle8Bits,\
lowerUpper8Bits, upper8Bits)\
(((((u32)lower8Bits) & LOWER8BIT_MASK)) | \
(((((u32)lowerMiddle8Bits) & LOWER8BIT_MASK) <<\
#define RETURN32BITS_FROM48BIT_VALUES(lower8_bits, lower_middle8_bits,\
lower_upper8_bits, upper8_bits)\
(((((u32)lower8_bits) & LOWER8BIT_MASK)) | \
(((((u32)lower_middle8_bits) & LOWER8BIT_MASK) <<\
LOWER_MIDDLE8BIT_SHIFT)) | \
(((((u32)lowerUpper8Bits) & LOWER8BIT_MASK) <<\
(((((u32)lower_upper8_bits) & LOWER8BIT_MASK) <<\
UPPER_MIDDLE8BIT_SHIFT)) | \
(((((u32)upper8Bits) & LOWER8BIT_MASK) <<\
(((((u32)upper8_bits) & LOWER8BIT_MASK) <<\
UPPER8BIT_SHIFT)))

/*
Expand Down Expand Up @@ -285,24 +285,26 @@ enum return_code_label {

/* Not sure if this all belongs here */

#define CHECK_RETURN_VALUE(actualValue, expectedValue, returnCodeIfMismatch,\
spyCodeIfMisMatch)
#define CHECK_RETURN_VALUE_RET(actualValue, expectedValue, returnCodeIfMismatch)
#define CHECK_RETURN_VALUE_RES(actualValue, expectedValue, spyCodeIfMisMatch)
#define CHECK_RETURN_VALUE_RET_VOID(actualValue, expectedValue,\
spyCodeIfMisMatch)

#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\
spyCodeIfMisMatch)
#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue,\
returnCodeIfMismatch)
#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue,\
returnCodeIfMismatch, spyCodeIfMisMatch)
#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue, maxValidValue,\
returnCodeIfMismatch)
#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue,\
returnCodeIfMismatch, spyCodeIfMisMatch)
#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, maxValidValue,\
returnCodeIfMismatch)
#define CHECK_RETURN_VALUE(actual_value, expected_value,\
return_code_if_mismatch, spy_code_if_mis_match)
#define CHECK_RETURN_VALUE_RET(actual_value, expected_value,\
return_code_if_mismatch)
#define CHECK_RETURN_VALUE_RES(actual_value, expected_value,\
spy_code_if_mis_match)
#define CHECK_RETURN_VALUE_RET_VOID(actual_value, expected_value,\
spy_code_if_mis_match)

#define CHECK_INPUT_PARAM(actual_value, invalid_value,\
return_code_if_mismatch, spy_code_if_mis_match)
#define CHECK_INPUT_PARAM_NO_SPY(actual_value, invalid_value,\
return_code_if_mismatch)
#define CHECK_INPUT_RANGE(actual_value, min_valid_value, max_valid_value,\
return_code_if_mismatch, spy_code_if_mis_match)
#define CHECK_INPUT_RANGE_NO_SPY(actual_value, min_valid_value,\
max_valid_value, return_code_if_mismatch)
#define CHECK_INPUT_RANGE_MIN0(actual_value, max_valid_value,\
return_code_if_mismatch, spy_code_if_mis_match)
#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actual_value, max_valid_value,\
return_code_if_mismatch)

#endif /* _GLOBALTYPES_H */
96 changes: 48 additions & 48 deletions drivers/staging/tidspbridge/hw/MMURegAcM.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,38 +33,38 @@
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32);\
data &= ~(MMU_MMU_SYSCONFIG_IDLE_MODE_MASK);\
newValue <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\
newValue &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\
newValue |= data;\
__raw_writel(newValue, base_address+offset);\
new_value <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\
new_value &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}

#define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32);\
data &= ~(MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK);\
newValue <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\
newValue &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\
newValue |= data;\
__raw_writel(newValue, base_address+offset);\
new_value <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\
new_value &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}

#define MMUMMU_IRQSTATUS_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\
(_DEBUG_LEVEL1_EASI(easil1_mmummu_irqstatus_read_register32),\
__raw_readl((base_address)+MMU_MMU_IRQSTATUS_OFFSET))

#define MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#define MMUMMU_IRQENABLE_READ_REGISTER32(base_address)\
Expand All @@ -74,9 +74,9 @@
#define MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#define MMUMMU_WALKING_STTWL_RUNNING_READ32(base_address)\
Expand All @@ -95,26 +95,26 @@
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32);\
data &= ~(MMU_MMU_CNTL_TWL_ENABLE_MASK);\
newValue <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\
newValue &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\
newValue |= data;\
__raw_writel(newValue, base_address+offset);\
new_value <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\
new_value &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}

#define MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32);\
data &= ~(MMU_MMU_CNTL_MMU_ENABLE_MASK);\
newValue <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\
newValue &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\
newValue |= data;\
__raw_writel(newValue, base_address+offset);\
new_value <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\
new_value &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}

#define MMUMMU_FAULT_AD_READ_REGISTER32(base_address)\
Expand All @@ -124,9 +124,9 @@
#define MMUMMU_TTB_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_TTB_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_TTB_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#define MMUMMU_LOCK_READ_REGISTER32(base_address)\
Expand All @@ -136,9 +136,9 @@
#define MMUMMU_LOCK_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#define MMUMMU_LOCK_BASE_VALUE_READ32(base_address)\
Expand All @@ -151,13 +151,13 @@
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(easil1_mmummu_lock_base_value_write32);\
data &= ~(MMU_MMU_LOCK_BASE_VALUE_MASK);\
newValue <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\
newValue &= MMU_MMU_LOCK_BASE_VALUE_MASK;\
newValue |= data;\
__raw_writel(newValue, base_address+offset);\
new_value <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\
new_value &= MMU_MMU_LOCK_BASE_VALUE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}

#define MMUMMU_LOCK_CURRENT_VICTIM_READ32(base_address)\
Expand All @@ -170,13 +170,13 @@
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32);\
data &= ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK);\
newValue <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\
newValue &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\
newValue |= data;\
__raw_writel(newValue, base_address+offset);\
new_value <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\
new_value &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}

#define MMUMMU_LOCK_CURRENT_VICTIM_SET32(var, value)\
Expand All @@ -192,33 +192,33 @@
#define MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#define MMUMMU_CAM_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_CAM_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CAM_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#define MMUMMU_RAM_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_RAM_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_RAM_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
register u32 newValue = (value);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32);\
__raw_writel(newValue, (base_address)+offset);\
__raw_writel(new_value, (base_address)+offset);\
}

#endif /* USE_LEVEL_1_MACROS */
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