---

yaml
---
r: 189819
b: refs/heads/master
c: 3d1bc86
h: refs/heads/master
i:
  189817: 3057c5f
  189815: 058fdba
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1b6a2b2d0ff2ced5fe608e0b2e13ccd2b7a283e5
+refs/heads/master: 3d1bc8626c7b17facfcb7fb5dee4686f47a1e75d

trunk/arch/arm/mach-mx5/mm.c

@@ -34,11 +34,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
 		.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
 		.length = MX51_DEBUG_SIZE,
 		.type = MT_DEVICE
-	}, {
-		.virtual = MX51_TZIC_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
-		.length = MX51_TZIC_SIZE,
-		.type = MT_DEVICE
 	}, {
 		.virtual = MX51_AIPS1_BASE_ADDR_VIRT,
 		.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
@@ -69,14 +64,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
  */
 void __init mx51_map_io(void)
 {
-	u32 tzic_addr;
-
-	if (mx51_revision() < MX51_CHIP_REV_2_0)
-		tzic_addr = 0x8FFFC000;
-	else
-		tzic_addr = 0xE0003000;
-	mxc_io_desc[2].pfn =  __phys_to_pfn(tzic_addr);
-
 	mxc_set_cpu_type(MXC_CPU_MX51);
 	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
@@ -85,5 +72,17 @@ void __init mx51_map_io(void)
 
 void __init mx51_init_irq(void)
 {
-	tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
+	unsigned long tzic_addr;
+	void __iomem *tzic_virt;
+
+	if (mx51_revision() < MX51_CHIP_REV_2_0)
+		tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
+	else
+		tzic_addr = MX51_TZIC_BASE_ADDR;
+
+	tzic_virt = ioremap(tzic_addr, SZ_16K);
+	if (!tzic_virt)
+		panic("unable to map TZIC interrupt controller\n");
+
+	tzic_init_irq(tzic_virt);
 }

trunk/arch/arm/plat-mxc/include/mach/mx51.h

@@ -14,7 +14,7 @@
  * FB100000	70000000	1M	SPBA 0
  * FB000000	73F00000	1M	AIPS 1
  * FB200000	83F00000	1M	AIPS 2
- * FA100000	8FFFC000	16K	TZIC (interrupt controller)
+ *		8FFFC000	16K	TZIC (interrupt controller)
  *         	90000000	256M	CSD0 SDRAM/DDR
  *         	A0000000	256M	CSD1 SDRAM/DDR
  *         	B0000000	128M	CS0 Flash
@@ -49,9 +49,8 @@
 #define MX51_GPU_BASE_ADDR		0x20000000
 #define MX51_GPU2D_BASE_ADDR		0xD0000000
 
-#define MX51_TZIC_BASE_ADDR		0x8FFFC000
-#define MX51_TZIC_BASE_ADDR_VIRT	0xFA100000
-#define MX51_TZIC_SIZE			SZ_16K
+#define MX51_TZIC_BASE_ADDR_TO1		0x8FFFC000
+#define MX51_TZIC_BASE_ADDR		0xE0000000
 
 #define MX51_DEBUG_BASE_ADDR		0x60000000
 #define MX51_DEBUG_BASE_ADDR_VIRT	0xFA200000
@@ -232,7 +231,6 @@
 #define MX51_IO_ADDRESS(x)					\
 	(void __iomem *)					\
 	(MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) :	\
-	MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :	\
@@ -246,9 +244,6 @@
 #define MX51_IRAM_IO_ADDRESS(x)  \
 	(((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
 
-#define MX51_TZIC_IO_ADDRESS(x)  \
-	(((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
-
 #define MX51_DEBUG_IO_ADDRESS(x)  \
 	(((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)