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yaml
---
r: 350732
b: refs/heads/master
c: eb8b8f2
h: refs/heads/master
v: v3
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Barry Song authored and Mike Turquette committed Jan 18, 2013
1 parent 543122c commit 5b3a8f8
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2 changes: 1 addition & 1 deletion [refs]
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---
refs/heads/master: 38a8b096f86dea54cc64f4daa3402d0c4f2df43e
refs/heads/master: eb8b8f2e7164b819ca35a3d6240198fdb98d0ef3
73 changes: 73 additions & 0 deletions trunk/Documentation/devicetree/bindings/clock/prima2-clock.txt
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* Clock bindings for CSR SiRFprimaII

Required properties:
- compatible: Should be "sirf,prima2-clkc"
- reg: Address and length of the register set
- interrupts: Should contain clock controller interrupt
- #clock-cells: Should be <1>

The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of prima2
clocks and IDs.

Clock ID
---------------------------
rtc 0
osc 1
pll1 2
pll2 3
pll3 4
mem 5
sys 6
security 7
dsp 8
gps 9
mf 10
io 11
cpu 12
uart0 13
uart1 14
uart2 15
tsc 16
i2c0 17
i2c1 18
spi0 19
spi1 20
pwmc 21
efuse 22
pulse 23
dmac0 24
dmac1 25
nand 26
audio 27
usp0 28
usp1 29
usp2 30
vip 31
gfx 32
mm 33
lcd 34
vpp 35
mmc01 36
mmc23 37
mmc45 38
usbpll 39
usb0 40
usb1 41

Examples:

clks: clock-controller@88000000 {
compatible = "sirf,prima2-clkc";
reg = <0x88000000 0x1000>;
interrupts = <3>;
#clock-cells = <1>;
};

i2c0: i2c@b00e0000 {
cell-index = <0>;
compatible = "sirf,prima2-i2c";
reg = <0xb00e0000 0x10000>;
interrupts = <24>;
clocks = <&clks 17>;
};
31 changes: 30 additions & 1 deletion trunk/arch/arm/boot/dts/prima2.dtsi
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Expand Up @@ -58,10 +58,11 @@
#size-cells = <1>;
ranges = <0x88000000 0x88000000 0x40000>;

clock-controller@88000000 {
clks: clock-controller@88000000 {
compatible = "sirf,prima2-clkc";
reg = <0x88000000 0x1000>;
interrupts = <3>;
#clock-cells = <1>;
};

reset-controller@88010000 {
Expand All @@ -85,6 +86,7 @@
compatible = "sirf,prima2-memc";
reg = <0x90000000 0x10000>;
interrupts = <27>;
clocks = <&clks 5>;
};
};

Expand All @@ -104,6 +106,7 @@
compatible = "sirf,prima2-vpp";
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
};
};

Expand All @@ -117,6 +120,7 @@
compatible = "powervr,sgx531";
reg = <0x98000000 0x8000000>;
interrupts = <6>;
clocks = <&clks 32>;
};
};

Expand All @@ -130,6 +134,7 @@
compatible = "sirf,prima2-video-codec";
reg = <0xa0000000 0x8000000>;
interrupts = <5>;
clocks = <&clks 33>;
};
};

Expand All @@ -149,12 +154,14 @@
compatible = "sirf,prima2-gps";
reg = <0xa8010000 0x10000>;
interrupts = <7>;
clocks = <&clks 9>;
};

dsp@a9000000 {
compatible = "sirf,prima2-dsp";
reg = <0xa9000000 0x1000000>;
interrupts = <8>;
clocks = <&clks 8>;
};
};

Expand All @@ -174,107 +181,123 @@
compatible = "sirf,prima2-nand";
reg = <0xb0030000 0x10000>;
interrupts = <41>;
clocks = <&clks 26>;
};

audio@b0040000 {
compatible = "sirf,prima2-audio";
reg = <0xb0040000 0x10000>;
interrupts = <35>;
clocks = <&clks 27>;
};

uart0: uart@b0050000 {
cell-index = <0>;
compatible = "sirf,prima2-uart";
reg = <0xb0050000 0x10000>;
interrupts = <17>;
clocks = <&clks 13>;
};

uart1: uart@b0060000 {
cell-index = <1>;
compatible = "sirf,prima2-uart";
reg = <0xb0060000 0x10000>;
interrupts = <18>;
clocks = <&clks 14>;
};

uart2: uart@b0070000 {
cell-index = <2>;
compatible = "sirf,prima2-uart";
reg = <0xb0070000 0x10000>;
interrupts = <19>;
clocks = <&clks 15>;
};

usp0: usp@b0080000 {
cell-index = <0>;
compatible = "sirf,prima2-usp";
reg = <0xb0080000 0x10000>;
interrupts = <20>;
clocks = <&clks 28>;
};

usp1: usp@b0090000 {
cell-index = <1>;
compatible = "sirf,prima2-usp";
reg = <0xb0090000 0x10000>;
interrupts = <21>;
clocks = <&clks 29>;
};

usp2: usp@b00a0000 {
cell-index = <2>;
compatible = "sirf,prima2-usp";
reg = <0xb00a0000 0x10000>;
interrupts = <22>;
clocks = <&clks 30>;
};

dmac0: dma-controller@b00b0000 {
cell-index = <0>;
compatible = "sirf,prima2-dmac";
reg = <0xb00b0000 0x10000>;
interrupts = <12>;
clocks = <&clks 24>;
};

dmac1: dma-controller@b0160000 {
cell-index = <1>;
compatible = "sirf,prima2-dmac";
reg = <0xb0160000 0x10000>;
interrupts = <13>;
clocks = <&clks 25>;
};

vip@b00C0000 {
compatible = "sirf,prima2-vip";
reg = <0xb00C0000 0x10000>;
clocks = <&clks 31>;
};

spi0: spi@b00d0000 {
cell-index = <0>;
compatible = "sirf,prima2-spi";
reg = <0xb00d0000 0x10000>;
interrupts = <15>;
clocks = <&clks 19>;
};

spi1: spi@b0170000 {
cell-index = <1>;
compatible = "sirf,prima2-spi";
reg = <0xb0170000 0x10000>;
interrupts = <16>;
clocks = <&clks 20>;
};

i2c0: i2c@b00e0000 {
cell-index = <0>;
compatible = "sirf,prima2-i2c";
reg = <0xb00e0000 0x10000>;
interrupts = <24>;
clocks = <&clks 17>;
};

i2c1: i2c@b00f0000 {
cell-index = <1>;
compatible = "sirf,prima2-i2c";
reg = <0xb00f0000 0x10000>;
interrupts = <25>;
clocks = <&clks 18>;
};

tsc@b0110000 {
compatible = "sirf,prima2-tsc";
reg = <0xb0110000 0x10000>;
interrupts = <33>;
clocks = <&clks 16>;
};

gpio: pinctrl@b0120000 {
Expand Down Expand Up @@ -507,17 +530,20 @@
pwm@b0130000 {
compatible = "sirf,prima2-pwm";
reg = <0xb0130000 0x10000>;
clocks = <&clks 21>;
};

efusesys@b0140000 {
compatible = "sirf,prima2-efuse";
reg = <0xb0140000 0x10000>;
clocks = <&clks 22>;
};

pulsec@b0150000 {
compatible = "sirf,prima2-pulsec";
reg = <0xb0150000 0x10000>;
interrupts = <48>;
clocks = <&clks 23>;
};

pci-iobg {
Expand Down Expand Up @@ -616,12 +642,14 @@
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8000000 0x10000>;
interrupts = <10>;
clocks = <&clks 40>;
};

usb1: usb@b00f0000 {
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8010000 0x10000>;
interrupts = <11>;
clocks = <&clks 41>;
};

sata@b00f0000 {
Expand All @@ -634,6 +662,7 @@
compatible = "sirf,prima2-security";
reg = <0xb8030000 0x10000>;
interrupts = <42>;
clocks = <&clks 7>;
};
};
};
Expand Down
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